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'''EPYC 7552''' is a {{arch|64}} [[48-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a {{amd|precision boost|boost}} frequency of up to 3.35 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 
'''EPYC 7552''' is a {{arch|64}} [[48-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a {{amd|precision boost|boost}} frequency of up to 3.35 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
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== Cache ==
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{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
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{{cache size
 +
|l1 cache=3 MiB
 +
|l1i cache=1.5 MiB
 +
|l1i break=48x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1.5 MiB
 +
|l1d break=48x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=24 MiB
 +
|l2 break=48x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=256 MiB
 +
|l3 break=16x16 MiB
 +
}}

Revision as of 16:45, 6 August 2019

Edit Values
EPYC 7552
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7552
Part Number100-000000076
MarketServer
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
ShopAmazon
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency2,200 MHz
Turbo Frequency3,350 MHz
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (7 dies)
Word Size64 bit
Cores48
Threads96
Max Memory4 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP200 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094
Succession

EPYC 7552 is a 64-bit 48-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a boost frequency of up to 3.35 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
48x32 KiB8-way set associative 
L1D$1.5 MiB
1,536 KiB
1,572,864 B
48x32 KiB8-way set associative 
L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  48x512 KiB8-way set associativewrite-back
L3$256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
  16x16 MiB  
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7552&oldid=93054"
Facts about "EPYC 7552 - AMD"
RDF feed
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
clock multiplier22 +
core count48 +
core family23 +
core nameRome +
designerAMD +
die count7 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7552 +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description8-way set associative +
l1d$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ size256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count2 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
microarchitectureZen 2 +
model number7552 +
nameEPYC 7552 +
packageSP3 + and FCLGA-4094 +
part number100-000000076 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
series7002 +
smp max ways2 +
socketSP3 + and LGA-4094 +
tdp200 W (200,000 mW, 0.268 hp, 0.2 kW) +
technologyCMOS +
thread count96 +
turbo frequency3,350 MHz (3.35 GHz, 3,350,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +