'''[[name::Crystal Well]]''' is the [[instance of::codename]] for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris ...two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...e [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==

== Cache == {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}

...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}

...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}

...emory. The 6167U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6287U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

*** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5). ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)

|l4=128 MiB |l4 per=package

|l4=128 MB |l4 per=package

|side cache=128 MiB |side cache per=package

|side cache=64 MiB |side cache per=package

...emory. The 6650U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6660U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

...U incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The P580 GPU is found in high-end mobile workstation (Xeon {{intel|Skylake {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}

|l4=128 MiB |l4 per=package

== Cache == {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}

...1.1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==

...GHz. This specific GPU also incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==

...950 MHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==

...of 1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==

...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...ntel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache. ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</

...IGP offered by Intel with 48 execution units and 64 MiB of dedicated side cache. Iris Plus 640 are found in selected high-end {{intel|Kaby Lake U|l=core}} ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</

...IGP offered by Intel with 48 execution units and 64 MiB of dedicated side cache. Iris Plus 650 are found in selected high-end {{intel|Kaby Lake U|l=core}} ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</

...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.

...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.

* Cache * Cache

| cache = Yes | l4 = 128 MiB

...corn/microarchitectures/arm3|arm/armv2|arm/armv2a|l1=ARM2|l2=ARM3|l3=ARMv2|l4=ARMv2a}} ...e improvements through a [[process shrink]] and the introduction of on-die cache. Thanks to those improvements, the processor was now capable of running at

...ors use {{intel|BGA-1356|Socket BGA-1528}} and incorporate 128 MiB of side cache. ** 128 MiB of eDRAM side cache

...with {{intel|Iris Pro Graphics 580}}) incorporate a large 128 MiB of side cache on-package. ...eader 1|cols=Launched, Discontinued, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Freque

...emory. The 6560U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6260U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6567U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6267U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6360U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

...emory. The 6157U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

== Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}

...ntel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, 1 Core, 2 Cores, Max Mem, GPU, %Frequency, Turbo, Turbo,

...U incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The 580 GPU is found in high-end mobile ({{intel|Skylake H|l=core}}) proce {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}

...Iris GT3 models, this GPU incorporates a larger 128 MiB of [[eDRAM]] side cache on-chip for added performance. This GPU also operates at an unusually high {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}

* Cache ** New 672 MiB/drawer of shared L4

...GHz. This particular [[GPU]] includes an additional 128 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...GHz. This particular [[GPU]] includes an additional 128 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...GHz. This particular [[GPU]] includes an additional 128 MiB of [[eDRAM]] [[L4$]]. == Cache ==

...GHz. This particular [[GPU]] includes an additional 128 MiB of [[eDRAM]] [[L4$]]. == Cache ==

|l4=128 MiB |l4 per=package

...rol Fabrics of each processor on dual-socket server platforms. S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders. XGBE is a backplane Ethern MA_DATA[39],CD55,MD_DQS_H[10],CP7,RSVD,AK15,RSVD,CT16,VDDCR_SOC,CL25,VSS,L4,VSS,BD14,VSS,CP15

...cache.<!--Naffziger2020--> GN-B1 CCDs contain one CCX with 32&nbsp;MiB L3 cache, the GMI2 signals are routed to the chip edge. These are serial, single-end S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders introduced on Type-1 proces

...[[DDR3]] and [[DDR4]]. DRAM ports are accessed in pairs, fetching 128 B [[cache lines]]/port-pair. Each port can address up to 16 logically independent DRA ...n Centaur communicate in a memory-channel-agnostic way. Operations such as cache-line reads/writes are sent to the chip as high-level commands. Scheduling i

|l4=960 MiB |l4 per=drawer

...can be used for I/O, e.g. connecting a GPU through a HT-PCI bridge, or for cache coherent inter-socket traffic using an AMD proprietary protocol, with flexi L1_CTLOUT_L[0],BC3,MA_DATA[28],D33,MC2_CS_L[1],BC37,MD_DATA[40],BT33,VDD,L4,VDDIO,AW30,VSS,P31,VSS,BL24

...s two ''Idle'' modes clock-gating the core. In one of these modes the data cache remains operational, snooping the SBUS to maintain coherency. {{abbr|GPR}}s D1_DM[1],AB18,NC,A1,VDDX,L4,VSS,U10

On dual socket (2P) systems the cache coherent xGMI links connect the Data Fabrics of each processor. Socket SP5 ...d accelerators with no local memory such as a NIC using the CXL.io and CXL.cache protocols) and CXL Type 3 devices (memory expanders, using the CXL.io and C