• c
  ...performing common tasks, such as: string handling, threading managements, memory management, and I/O processing; this set of functions is called the '''{{C ** {{C|Program structure}}
  5 KB (790 words) - 13:36, 2 October 2017
• mips/coprocessor 0
  | [[Index register - MIPS|Context]] || 0 || rowspan="8" | memory management (TLB) | [[BadVAddr register - MIPS|BadVAddr]] || 8 || Program address of the violation
  3 KB (384 words) - 10:11, 19 February 2018
• mirc/component object model
  ...t provides methods and properties associated with the windows media player program ;0 will return the total number of elements (memory sticks in this case)
  27 KB (3,608 words) - 11:41, 25 October 2018
• Lua
  ...age. Lua is generally considered a very fast, very simple, and very small (program size) making it highly embeddable and portable. The official Lua implementa ...eed to compile the source at run-time. This ability also allows for faster program loading but not necessarily smaller lua programs.<ref>[http://www.lua.org/m
  3 KB (429 words) - 23:30, 1 March 2014
• c/concurrency
  ...language]] introduced the semantics necessary for writing a multithreaded program starting with the [[C11]] standard. The standard also specified a set of fu ...<code>thrd_nomem</code> will be returned indicating insufficient amount of memory or failure to honor the request.
  2 KB (246 words) - 07:30, 4 January 2015
• intel/mcs-4/4004
  |max memory addr=4 kB ...nstructions per second. The chip was capable of accessing 4KB of [[program memory]] and 640 bytes of RAM. The 4004 was part of the [[Intel MCS-4]] system.
  5 KB (748 words) - 21:37, 21 November 2021
• intel/core i7
  |?has ecc memory support |?has ecc memory support
  43 KB (5,739 words) - 21:30, 22 April 2024
• microprocessor
  ...ogic unit]] (ALU), [[floating point unit]] (FPU), [[control unit]] (CU), [[memory management unit]] (MMU), [[interrupt handler|interrupts]], [[input/output]] ...nt on the characteristics of the [[instruction set]] it operates on. Every program that runs on that microprocessor is therefore bound by that [[instruction s
  8 KB (1,149 words) - 00:41, 16 September 2019
• programming language
  ...ormal language]] along with [[computational semantics]] used for writing [[program]]s, which instruct a machine (physical or virtual) to perform some kind of ...computer was designed to be digital, programmable using punch cards, with memory for up to 1000 numbers. Had it been completed, it would have been the first
  2 KB (220 words) - 01:42, 10 July 2016
• novix/nc4016
  ...hree separate modules were required: for the return stack, data stack, and program and data stack.
  2 KB (257 words) - 16:31, 13 December 2017
• c/const
  ...heir declaration must not be assigned to a value during the execution of a program. ...-qualified objects is to allow compilers to place such values in read-only memory. Additionally const-qualified objects might allow compilers to perform some
  2 KB (297 words) - 07:47, 4 January 2015
• fairchild/pps-25
  | {{\|3808}} || Memory | {{\|3810}} || Program ROM
  2 KB (291 words) - 23:48, 10 July 2017
• microprocessors used in spacecrafts
  ! style="width: 25%;" | System !! Processor !! Frequency !! Memory !! Weight ...i Spacecraft]] was part of Project Gemini, NASA's second human spaceflight program.
  11 KB (1,334 words) - 18:26, 10 May 2019
• gemini guidance computer
  * 39-bit words memory, each composed of three 13-bit "syllables" * ferrite core memory of 4096 words<ref>[http://history.nasa.gov/computers/Ch1-2.html ''Computers
  4 KB (592 words) - 15:40, 23 November 2015
• program counter
  ...ion counter'''/'''pointer''' (IC/IP) is a [[counter]] that points to the [[memory location]] that stores the current or future instruction. Depending on the
  502 bytes (65 words) - 18:42, 24 June 2017
• amd/am2900
  ...roduce any multiple of 4-bit wide data path (8, 12, 16, 32, etc. bits) and memory address for use in larger systems. | {{\|AM2930}} || Program control unit, 4-bit slice address controller for memories || 28
  9 KB (1,061 words) - 22:55, 18 June 2019
• fairchild/9400
  | {{fairchild|9403}} || Series/Parallel [[FIFO]] (Buffer Memory) | {{fairchild|9406}} || Program Stack (16x4-bit [[LIFO]])
  2 KB (223 words) - 23:04, 5 October 2017
• fairchild/4700
  | {{\|4703}} || Series/Parallel [[FIFO]] (Buffer Memory) | {{\|4706}} || Program Stack
  3 KB (283 words) - 17:18, 12 December 2016
• microcontroller
  .... This usually includes the [[CPU]], [[program memory|program]] and [[data memory]], [[programmable I/O|programmable]] [[serial communication|serial]] and [[
  2 KB (344 words) - 15:51, 21 March 2024
• general instrument/8000
  | {{\|LP 6000}} || [[Program Memory]] (PM) | {{\|LP 1000}} || Memory interface chip (MIC)
  2 KB (185 words) - 00:33, 19 May 2016
• rockwell international/pps-4
  ...p microcomputer) was actually a [[microcontroller]], including the program memory internally.
  3 KB (359 words) - 17:26, 19 May 2016
• motorola/mc14500
  | {{motorola|MCM7641}} || Program Counter ...as done externally, in theory at least, this MPU can support any amount of memory needed.
  4 KB (538 words) - 10:44, 22 May 2018
• rockwell international/pps-4-1
  ...ockwell|PPS-4/2}} with the addition of a [[clock generator]] and [[program memory]] incorporated internally, making it a single-chip system (hence the "/1").
  2 KB (219 words) - 01:00, 19 May 2016
• amd/am29100
  ...29112}} [[microsequencer]] or custom logic) to handle [[subroutines]], and memory access.
  3 KB (323 words) - 11:26, 15 August 2017
• intel/mcs-8/isa
  | format = Register-Memory ...n operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmet
  13 KB (2,079 words) - 09:11, 29 September 2019
• intel/mcs-8/8008
  |max memory=16 KiB ...500 kHZ, had 8-bit data words, and could address 16KB of memory (14-bits [[program counter|PC]]). Originally commissioned by [[Datapoint Corporation]] (then C
  2 KB (254 words) - 19:24, 23 March 2022
• intel/microarchitectures/skylake (client)
  ** Memory Subsystem * Memory
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/core i5
  |?has ecc memory support |?has ecc memory support
  34 KB (4,663 words) - 20:38, 20 February 2023
• amd/am486
  |?max memory#GB |?max memory#GB
  13 KB (1,897 words) - 09:30, 21 July 2021
• mathstar/builder
  ...(MAC), and [[Register File]] (RF). The control program guides the overall program execution and the datapath setup. Datapath is {{arch|16}} but may be combin ...l !! Objects !! Parallel I/O Inter. !! Serial I/O Trans. !! GPIO !! 36-bit Memory Cntr
  5 KB (596 words) - 21:23, 19 November 2017
• amd/microarchitectures/zen
  === Memory Hierarchy === ...n all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. T
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ** Memory subsystem * <code>{{x86|MCOMMIT}}</code> - Commit stores to memory
  57 KB (8,701 words) - 22:11, 9 October 2022
• acorn/microarchitectures/arm1
  ...simplify system design, these clocks may be stretched to work in-sync with memory access times. ...he address register gets sent through the address pins and is fetched from memory.
  12 KB (1,886 words) - 12:56, 14 January 2021
• arm/26-bit architectures
  ...unter]] was 24 bits allowing for a 26-bit address space of up to 64 MiB of memory. The other bits were used for the {{arm|Processor Status Register}}. With t ...raise a memory access exception. On the {{arm|32-bit architectures}}, the program counter was extended to 30 bits, allowing the full 4 GiB address space to b
  3 KB (535 words) - 09:13, 18 February 2021
• arm/armv1
  ...[[program counter]] allowing for a 26-bit address space of up to 64 MiB of memory. ...oad Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}}
  10 KB (1,558 words) - 15:07, 2 July 2017
• acorn/microarchitectures/arm2
  ...ements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a * > 2x MIPS when not bottlenecked by memory
  14 KB (2,093 words) - 04:42, 10 July 2018
• arm holdings/microarchitectures/arm6
  ** Can map 4 GiB of memory ** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]]
  11 KB (1,679 words) - 18:49, 18 May 2023
• intel/microarchitectures/skylake (server)
  ** Memory Subsystem * Memory
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/cores/coffee lake h
  * Dual-channel Memory |?has ecc memory support
  5 KB (648 words) - 17:43, 6 December 2018
• bitmain/sophon/bm1680
  |max memory=16 GiB The chip consists of five subsystems: [[NPU]], [[MCU]], Chip Link, Memory, and Peripherals.
  4 KB (603 words) - 09:59, 11 August 2018
• cve/cve-2017-5753
  ...of {{cve|CVE-2017-5715}} (Spectre, Variant 2) in order to cause a correct program to lead to this (Variant 1) vulnerability by making the microprocessor take ...not reverted which can be detected and used to find a byte of the victim's memory.
  12 KB (1,869 words) - 10:01, 27 February 2019
• intel/microarchitectures/polaris
  ...hip as a direct consequence of their {{intel|Tera-scale Computing Research Program}} and is the basis of Intel's later research projects which paved the way f ...of their nearest neighbors as well as directly to the [[stacked]] [[SRAM]] memory.
  16 KB (2,552 words) - 23:22, 17 May 2019
• google/pixel visual core
  ...tom [[VLIW]] ISA designed to expose maximum instruction-level and multiple program data parallelism. Though the chip supports 32-bit integers, the native oper <tr><th>Field</th><td>Scalar</td><td>Math</td><td>Memory</td><td>Imm</td><td>MemImm</td></tr>
  4 KB (617 words) - 10:03, 19 April 2019
• cavium/microarchitectures/vulcan
  ** Memory Subsystem * Memory Controller
  17 KB (2,449 words) - 22:11, 4 October 2019
• supercomputers/summit
  ...stimated to have cost around $200 million as part of the CORAL procurement program. Summit has over 10 [[petabytes]] of memory.
  9 KB (1,496 words) - 20:39, 21 July 2019
• supercomputers/astra
  ...prototypes commissioned by the [[U.S. Department of Energy]] as part of a program that evaluates the feasibility of emerging high-performance computing archi ...28 cores]] operating at 2 GHz. Astra has close around 700 [[terabytes]] of memory and uses a 3-level fat tree [[interconnect architecture|interconnect]].
  8 KB (1,133 words) - 23:36, 2 June 2020
• arm/aarch64
  | Exception Link Register<br>([[program counter|PC]]) || || ELR_EL1 || ELR_EL2 || ELR_EL3 ...e smallest page supported as well as the size of the translation tables in memory. Which of the three supported is up to the implementation.
  4 KB (661 words) - 20:26, 2 May 2019
• intel/configurable spatial accelerator
  ...ssing elements (PEs) tiles along with an on-die interconnect network and a memory interface. The array of processing elements can include integer arithmetic === Memory ===
  14 KB (2,130 words) - 20:19, 2 October 2018
• snia/npm
  ...etween various user space and kernel components supporting [[storage-class memory]]. ...rking Group (TWG) is the group heading the specification of the persistent memory programming model.
  4 KB (637 words) - 14:41, 19 November 2018
• intel/cores/coffee lake hr
  * Dual-channel Memory |?has ecc memory support
  4 KB (507 words) - 07:45, 5 May 2019

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