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Exynos 9825
General Info
Designer	Samsung, ARM Holdings
Manufacturer	Samsung
Model Number	9825
Market	Mobile
Introduction	August 6, 2019 (announced) 2019 (launched)
General Specs
Family	Exynos
Series	Exynos 9
Locked	No
Frequency	2730 MHz, 2400 MHz, 1950 MHz
Microarchitecture
ISA	ARMv8.2 (ARM)
Microarchitecture	M4, Cortex-A75, Cortex-A55
Core Name	Cheetah, Cortex-A75, Cortex-A55
Process	7 nm
Technology	CMOS
MCP	Yes
Word Size	64 bit
Cores	8
Threads	8
Max Memory	12 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	0.915 V-1.13 V
TDP	5 W
cTDP down	5 W
cTDP down frequency	2730 MHz
cTDP up	8 W
cTDP up frequency	3016 MHz
OP Temperature	40 °C – 115 °C
Tjunction	115 – 115
Succession
Exynos 9810 Exynos 990
Contemporary
Exynos 9820

Exynos 9825 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2019. The processor is fabricated on Samsung's 7nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 4 big cores running at 2730 to 3016 MHz, 2 Cortex-A75 middle cores at 2400 MHz, and 4 Cortex-A55 little cores at 1950 to 2106 MHz. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9825 incorporates an LTE modem supporting cat 20 download and upload.

Cache

Main articles: Mongoose 4 § Cache and Cortex-A76 § Cache

For the Mongoose 4 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2x512 KiB 16-way set associative   L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB

For the Cortex-A75 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 16-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3600 Supports ECC No Max Mem 12 GiB Frequency 1800 MHz Controllers 4 Channels 4 Width 16 bit Max Bandwidth 26.82 GiB/s 27,463.68 MiB/s 28.798 GB/s 28,797.756 MB/s 0.0262 TiB/s 0.0288 TB/s Bandwidth Single 6.71 GiB/s Double 13.41 GiB/s Quad 26.82 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G76 Designer ARM Holdings Execution Units 12 Max Displays 2 Frequency 754 MHz 0.754 GHz 754,000 KHz Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Codec	Encode	Decode
HEVC (H.265)	✔	✔
MPEG-4 AVC (H.264)	✔	✔
VP9	✔	✔

All at 4K UHD 150fps.

Wireless

Wireless Communications
Cellular
4G	LTE Advanced UE Cat DL 20 (2000 Mbps) UE Cat UL 20 (316 Mbps)

ISP

• 22MP Rear
• 22MP Front
• 16MP+16MP Dual

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension Crypto Cryptographic Extension FP Floating-point Extension

Utilizing devices

• Samsung Galaxy Note 10
• Samsung Galaxy Note 10+