Page title matches

• insulated-gate field-effect transistor
  20 bytes (2 words) - 10:53, 14 November 2015

Page text matches

• 3 µm lithography process
  | process 1 transistor = Planar | process 1 gate len = 3 µm
  3 KB (314 words) - 23:04, 20 May 2018
• multiplexer
  ...e input from ''A'' should pass to the output while the bottom transmission gate does the same for the ''B'' input. A single [[inverter]] is used to invert A 2:1 MUX can also be built using an [[AOI222]] gate.
  10 KB (1,445 words) - 11:53, 18 November 2018
• buffer gate
  {{title|Buffer Gate}}{{logic gate |title = Buffer Gate
  3 KB (454 words) - 16:15, 11 August 2018
• mosfet
  {{title|MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor}}[[File:Electronic component mosfets.jpg|thumb|[[discrete logic chips|Indiv ...oth digital and analog circuits. Because originally the [[controlling gate|gate]] was made from metal, the name metal-oxide semiconductor (MOS) got stuck.
  8 KB (1,362 words) - 23:38, 17 November 2015
• inverter
  ...ts design onto more complex structures such as [[NOR gate|NOR]] and [[NAND gate|NAND]] gates. The electrical behavior of much bigger and complex circuitry ! colspan="2" | NOT Gate
  6 KB (983 words) - 04:50, 8 November 2015
• 7400 series
  While the original series was designed as [[transistor-transistor logic|TTL]] logic chips, over the years, a large number of sub-families hav ...- When no indicator is found, this implies it's the original [[transistor-transistor logic|TTL]]
  7 KB (851 words) - 20:53, 29 July 2021
• cmos
  ...ntary [[mosfet|MOS]] [[transistor]]s - [[pmos transistor|pMOS]] and [[pMOS transistor|nMOS]]. CMOS is the dominant technology used for [[VLSI]] and [[ULSI]] cir ...nd [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V_DD - V_t we get
  7 KB (1,159 words) - 21:01, 8 February 2019
• bicmos
  ...nalog and digital logic circuits from both [[CMOS]] and [[bipolar junction transistor|Bipolar]] semiconductor technologies. ...ed speed over [[CMOS]] and lower power dissipation than [[bipolar junction transistor|bipolar]] by combining both technologies on a single [[die]]. BiCMOS fabric
  2 KB (329 words) - 08:33, 16 January 2019
• logic gate
  {{confuse|ideal logic gate}} ...emented using discrete components such as [[resistor]]s, [[diode]]s, and [[transistor]]s.
  5 KB (838 words) - 11:19, 10 February 2020
• gate universality
  '''Gate universality''' is a concept that refers to individual [[logic gates]], pri ...t sets of [[pMOS transistor|pMOS]] and [[nMOS transistor|nMOS]] pairs of [[transistor]]s.
  903 bytes (132 words) - 00:34, 8 December 2015
• pass-transistor logic
  ...a class of [[non-restoring logic]] [[logic families|families]] that use [[transistor]]s as switches such that the output [[logic level]]s directly come from the ...ogic with reduced number of active devices thereby producing lower overall transistor count and a reduction in associated interconnections. The obvious drawback
  767 bytes (115 words) - 22:32, 25 November 2015
• Manchester carry-chain adder
  ...of the chain results in a delay that is quadratic with the number of bits. Transistor sizing was performed to improve performance. The details are elaborated on ...s with the nubmer of stages (the critical path involves a series propagate transistor for each bit); so the delay will grow like n2.The worst case delay depends
  2 KB (421 words) - 23:00, 8 December 2015
• technology node
  ...on of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's ...ahead). At those nodes the "process node" was effectively larger than the gate length.
  8 KB (1,225 words) - 13:48, 14 December 2022
• 28 nm lithography process
  | process 1 transistor = Planar | process 1 gate len = 24 nm
  6 KB (711 words) - 17:01, 26 March 2019
• 32 nm lithography process
  | process 1 transistor = Planar | process 1 gate len = 30 nm
  10 KB (1,090 words) - 19:14, 8 July 2021
• 14 nm lithography process
  ...name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and has be | process 1 transistor = FinFET
  17 KB (2,243 words) - 19:32, 25 May 2023
• 45 nm lithography process
  ...Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process. |Contacted Gate Pitch
  5 KB (602 words) - 05:51, 20 July 2018
• intel/microarchitectures/bonnell
  ...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. [[File:intel 45nm transistor.png|215px|left]]
  38 KB (5,468 words) - 20:29, 23 May 2019
• 20 µm lithography process
  ...standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages and dual in-line packages. |Contacted Gate Pitch
  902 bytes (119 words) - 23:04, 20 May 2018
• 22 nm lithography process
  ...name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using ...ransistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new pro
  7 KB (891 words) - 09:52, 25 November 2020

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