The Manchester Carry-Chain Adder is a chain of pass-transistors that are used to implement the carry chain. During precharge, all intermediate nodes (e.g. Cout0) are charged to Vdd. During the evaluation phase, Cout_k is discharged if there is an incoming carry Cin0 and the previous propagate signals (P0...Pk-1) are high. Only 4 diffusion capacitances are present at each node, but the distributed RC-nature of the chain results in a delay that is quadratic with the number of bits. Transistor sizing was performed to improve performance. The details are elaborated on in the design strategy section. The Manchester carry chain was designed using dynamic logic and implements the following logical function:

Coi=Gi+PiCoi−1

where Co is the carry out.

Design Strategy

The good thing about Manchester Carry Chains is that there is no gate between stages. Only 4 diffusion capacitances are present at each node The bad news is that the number of series transistors increases with the nubmer of stages (the critical path involves a series propagate transistor for each bit); so the delay will grow like n2.The worst case delay depends on the generation of carry-Propagate signals. Transistors were sized in the following manner to improve performance: Consider the worst case delay of the following carry chain: Elmore delay is given by . Therefore, the delay is tp = 0.69(R1C1 + (R1+R2)C2 + (R1+R2+R3)C3 + (R1+R2+R3+R4)C4 + (R1+R2+R3+R4+R5)C5 + (R1+R2+R3+R4+R5+R6)C6. Since R6 appears 6 times in the expression, it makes sense to minimize this first. When we reduce R by a factor of k, capacitance at each stage increases by a factor of k and area is increased. At k = 1.5, area is increased by 3.5x BUT delay is reduced by 40%. This is a perfect example of the tradeoff between speed and area. Transistor sizing was designed such that the resistance of each consecutive transistor in the chain was slightly higher than the last to minimize delay (by a factor of 1.5 - reducing delay by 40% as calculated using Elmore's delay). The pull-up transistors were sized in a similar way to provide the appropriate resistance to their respective pull-down transistors. The test bench schematic and simulation results are below. Due to the large number of signals, only the outputs are displayed as this gives us enough information about the delays incurred by the circuit.

Quantitative Metrics

- stuff about the critical path*** The circuit acheived rise and fall times of roughly 0.7ns.

Schematics

Circuit Schematic

Circuit Symbol