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Vanilla-5 µarch
General Info
Arch Type	CPU
Designer	University of Michigan, University of California, Cornell University, University of California
Manufacturer	TSMC
Process	16 nm
Pipeline
Type	Pipelined
OoOE	No
Speculative	No
Reg Renaming	No
Stages	5
Decode	1
Instructions
ISA	RISC-V
Extensions	Integer, Multiply
Cache
L1I Cache	4 KiB/core
L1D Cache	4 KiB/core

Vanilla-5 is a custom RISC-V core microarchitecture designed specifically for the Celerity SoC.