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EPYC 7552
General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Model Number	7552
Part Number	100-000000076
Market	Server
Introduction	August 7, 2019 (announced) August 7, 2019 (launched)
Release Price	$4025.00
Shop	Amazon
General Specs
Family	EPYC
Series	7002
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	3,350 MHz
Clock multiplier	22
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Rome
Core Family	23
Process	7 nm, 14 nm
Technology	CMOS
MCP	Yes (7 dies)
Word Size	64 bit
Cores	48
Threads	96
Max Memory	4 TiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Electrical
TDP	200 W
Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094
Succession
EPYC 7551

EPYC 7552 is a 64-bit 48-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a boost frequency of up to 3.35 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 3 MiB 3,072 KiB 3,145,728 B L1I$ 1.5 MiB 1,536 KiB 1,572,864 B 48x32 KiB 8-way set associative   L1D$ 1.5 MiB 1,536 KiB 1,572,864 B 48x32 KiB 8-way set associative   L2$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     48x512 KiB 8-way set associative write-back L3$ 192 MiB 196,608 KiB 201,326,592 B 0.188 GiB     12x16 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3200 Supports ECC Yes Max Mem 4 TiB Controllers 8 Channels 8 Max Bandwidth 190.7 GiB/s 195,276.8 MiB/s 204.763 GB/s 204,762.566 MB/s 0.186 TiB/s 0.205 TB/s Bandwidth Single 23.84 GiB/s Double 47.68 GiB/s Quad 95.37 GiB/s Hexa 143.1 GiB/s Octa 190.7 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 4.0 Max Lanes: 128 Configuration: x16, x8

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SME Secure Memory Encryption TSME Transparent SME SEV Secure Encrypted Virtualization SenseMI SenseMI Technology Boost 2 Precision Boost 2