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Cortex-A15 - Microarchitectures - ARM
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Cortex-A15 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | September 8, 2010 |
Succession | |
Cortex-A15 (codename Eagle) is the successor to the Cortex-A9, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the Cortex-A12 (and the A17), also the successor to the Cortex-A9, target high-efficiency.
Contents
Architecture
Key changes from Cortex-A9
- 28 nm process (from 40 nm)
- Longer pipeline (15+, up from 9-12)
- 1.25x frequency (2.5 GHz, up from 2 GHz)
- 6x larger return stack size (48 entries, up from 8)
- Integer
- Hardware division support
- Hardware Fused Multiply-Accumulate
- VFPv4 (from VFPv3)
- NEONv2 (from NEON)
- Memory subsystem
- Level 1 instruction cache switched to PIPT (from VIPT)
- Level 1 instruction cache reduced to 2-way set associative (down from 4-way)
- Level 1 data cache reduced to 2-way set associative (down from 4-way)
- Added LPAE support
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Block Diagram
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Memory Hierarchy
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Licensees
Arm named the following companies as licensees.
Facts about "Cortex-A15 - Microarchitectures - ARM"
codename | Cortex-A15 + |
designer | ARM Holdings + |
first launched | September 8, 2010 + |
full page name | arm holdings/microarchitectures/cortex-a15 + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A15 + |