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ARM2 µarch
General Info
Arch Type	CPU
Designer	ARM Holdings
Manufacturer	VLSI Technology, Sanyo
Introduction	1986
Process	2 µm
Core Configs	1
Pipeline
Type	Scalar, Pipelined
Stages	3
Decode	1-way
Instructions
ISA	ARMv2
Cache
L1I Cache	0 KiB/Core
L1D Cache	0 KiB/Core
Succession
ARM1 ARM3

ARM2 is the second ARM implementation designed by ARM Holdings (then Acorn Computers) as a successor to the ARM1. Introduced in 1986, the ARM2 brings a number of major improvements over its predecessor.

Overview

See also: arm/history and ARM's History

Introduced in 1986, the ARM2 is a reimplementation of the ARM1 on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory.

Process Technology

See also: 2 µm process

ARM2 chips were manufactured by VLSI Technology and Sanyo on a 2 µm double-level metal CMOS process.

Architecture

Key changes from ARM1

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Block Diagram

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Core

Pipeline

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Die Shot

• 2 µm process
• 27,000 transistors
• ~5 mm x 5 mm
• 25 mm² die size

All ARM2 Chips

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References

• Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.