From WikiChip
Exynos 9825 - Samsung
< samsung‎ | exynos
Revision as of 06:08, 16 March 2023 by 189.40.89.28 (talk)

Edit Values
Exynos 9825
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9825
MarketMobile
IntroductionAugust 6, 2019 (announced)
2019 (launched)
General Specs
FamilyExynos
SeriesExynos 9
LockedNo
Frequency2@3016 MHz, 2@2400 MHz, 4@2106 MHz
Clock multiplier30
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureM4, Cortex-A75, Cortex-A55
Core NameCheetah, Cortex-A75, Cortex-A55
Process7 nm
TechnologyCMOS
MCPYes
Word Size64 bit
Cores8
Threads8
Max Memory12 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.915v-1.13v
TDP5w
cTDP down5W
cTDP down frequency2730MHz
cTDP up8W
cTDP up frequency3016MHz
OP Temperature40 – 115
Tjunction115 – 115
Succession
Contemporary
Exynos 9820

Exynos 9825 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2019. The processor is fabricated on Samsung's 7nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 4 big cores and 2 Cortex-A75 middle cores and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9825 incorporates an LTE modem supporting cat 20 download and upload.

Cache

Main articles: Mongoose 4 § Cache and Cortex-A76 § Cache

For the Mongoose 4 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB16-way set associative 
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB  

For the Cortex-A75 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
2x64 KiB16-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associative 


For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3600
Supports ECCNo
Max Mem12 GiB
Frequency1800 MHz
Controllers4
Channels4
Width16 bit
Max Bandwidth26.82 GiB/s
27,463.68 MiB/s
28.798 GB/s
28,797.756 MB/s
0.0262 TiB/s
0.0288 TB/s
Bandwidth
Single 6.71 GiB/s
Double 13.41 GiB/s
Quad 26.82 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G76
DesignerARM Holdings
Execution Units12Max Displays2
Frequency600 MHz
0.6 GHz
600,000 KHz
OutputDSI
Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Codec Encode Decode
HEVC (H.265) ✔ ✔
MPEG-4 AVC (H.264) ✔ ✔
VP9 ✔ ✔

All at 4K UHD 150fps.

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL20 (2000 Mbps)
UE Cat UL20 (316 Mbps)

ISP

  • 22MP Rear
  • 22MP Front
  • 16MP+16MP Dual

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices

  • Samsung Galaxy Note 10
  • Samsung Galaxy Note 10+
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/9825&oldid=101226"
Facts about "Exynos 9825 - Samsung"
RDF feed
base frequency2,730 MHz (2.73 GHz, 2,730,000 kHz) +, 2,400 MHz (2.4 GHz, 2,400,000 kHz) + and 1,950 MHz (1.95 GHz, 1,950,000 kHz) +
core count8 +
core nameCortex-A75 +, Cortex-A55 + and Cheetah +
core voltage (max)1.13 V (11.3 dV, 113 cV, 1,130 mV) +
core voltage (min)0.915 V (9.15 dV, 91.5 cV, 915 mV) +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedAugust 6, 2019 +
first launched2019 +
full page namesamsung/exynos/9825 +
has 4g supporttrue +
has ecc memory supportfalse +
has locked clock multiplierfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G76 +
integrated gpu base frequency754 MHz (0.754 GHz, 754,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units12 +
is multi-chip packagetrue +
isaARMv8.2 +
isa familyARM +
l1$ size192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 16-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative + and 8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate2019 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
max memory12,288 MiB (12,582,912 KiB, 12,884,901,888 B, 12 GiB, 0.0117 TiB) +
max memory bandwidth26.82 GiB/s (27,463.68 MiB/s, 28.798 GB/s, 28,797.756 MB/s, 0.0262 TiB/s, 0.0288 TB/s) +
max memory channels4 +
max operating temperature115 °C +
microarchitectureCortex-A75 +, Cortex-A55 + and M4 +
min junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
min operating temperature40 °C +
model number9825 +
nameExynos 9825 +
process7 nm (0.007 μm, 7.0e-6 mm) +
seriesExynos 9 +
smp max ways1 +
supported memory typeLPDDR4X-3600 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
tdp down5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
tdp down frequency2,730 MHz (2.73 GHz, 2,730,000 kHz) +
tdp up8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp up frequency3,016 MHz (3.016 GHz, 3,016,000 kHz) +
technologyCMOS +
thread count8 +
used bySamsung Galaxy Note 10 + and Samsung Galaxy Note 10+ +
user equipment category downlink20 +
user equipment category uplink20 +
word size64 bit (8 octets, 16 nibbles) +