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• fairchild/f8
  | {{\|3851}} || [[ROM]] ! Part !! I/O Lines !! Regs !! RAM !! ROM !! Description
  2 KB (172 words) - 17:18, 12 December 2016
• intel/mcs-80
  | {{intel|2716}} || 2048x8 bit || EPROM (pin compatible with {{intel|2316E}} ROM) | {{intel|8308}} || 1024x8 bit || MOS ROM (pin compatible with {{intel|8708}} PROM)
  4 KB (406 words) - 16:10, 26 January 2019
• intel/microarchitectures/bonnell
  ...directly. Those selected few get diverted into the '''micro-code sequencer ROM''' ('''MSROM''') for decoding producing much more sane RISCish instructions
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/haswell (client)
  ...µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads.
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq ...he two threads and can also hold pointers to the [[microcode sequencer]] [[ROM]]. It's also virtually addressed and is a strict subset of the L1 instructi
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq
  79 KB (11,922 words) - 06:46, 11 November 2022
• exponential technology/x704
  ...ify their ROM. In mid-April Apple agreed to provide clones with a modified ROM but at higher charge (supposedly proportional to the processor speed used). ...ount of time. As a last straw; Apple never delivered the promised modified ROM.
  8 KB (1,228 words) - 20:49, 2 June 2019
• p-rating
  ...s CD-ROM (PC Magazine Labs)]; Ziff-Davis Publishing Group PC Benchmarks CD-ROM, including Winstone 96 and Winbench 96 benchmarks. From PC Magazine Labs, i
  3 KB (456 words) - 06:30, 8 July 2020
• amd/microarchitectures/zen
  ...at end up emitting more than two macro-ops will be redirected to microcode ROM. When this happens the OP Queue is stalled (possibly along with the decoder ...a secured kernel with the firmware which sits externally (e.g., on an SPI ROM). The secure processor is responsible for the cryptographic functionalities
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ...nd at this stage probably represented by a macro-op containing a microcode ROM entry address. In the Zen/Zen+ microarchitecture AVX-256 instructions which ...f macro-ops from the micro-op queue. A patch RAM supplements the microcode ROM and can hold additional sequences. The microcode sequencer supports branchi
  57 KB (8,701 words) - 22:11, 9 October 2022
• mos technology
  *{{mos|6530}} ROM/RAM I/O Timer (RRIOT)
  2 KB (269 words) - 18:40, 31 August 2021
• acorn/microarchitectures/arm1
  ...number of separate units is because the ARM1 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w
  12 KB (1,886 words) - 12:56, 14 January 2021
• dec/microarchitectures/alpha 21064
  * Directly serial ROM interface
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  ...number of separate units is because the ARM2 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w
  14 KB (2,093 words) - 04:42, 10 July 2018
• renesas/r-car/h2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (420 words) - 16:32, 13 December 2017
• renesas/r-car/m2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/e2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/v2h
  * Flash ROM and SRAM Data bus width: 8/16 bit
  2 KB (346 words) - 16:32, 13 December 2017
• ti/tms1000/tms1099
  The TMS1099JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 64x4 bits of RAM, 8 bits o This ROM-less version addresses 1024 x 8 bits on an external memory (EPROM).
  824 bytes (121 words) - 14:56, 13 December 2017
• ti/tms1000/tms1098
  The TMS1098JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 128x4 bits of RAM, 8 bits This ROM-less version addresses 2048 x 8 bits on an external memory (EPROM).
  900 bytes (128 words) - 14:56, 13 December 2017

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