• amd/packages/socket am3
  !Signal!!Description |CLKIN_H/L||200 MHz Differential PLL Reference Clock
  12 KB (1,960 words) - 12:23, 18 July 2020
• amd/packages/ft1
  !Signal!!Type!!Description |M_CKE[1:0]||O-IO-S||DRAM Clock Enable
  14 KB (2,611 words) - 00:31, 4 April 2022
• amd/packages/super socket 7
  ...tended battery life, higher core frequencies, and raised the frontside bus clock to 100 MHz. For mobile and embedded processors AMD developed the {{\\|CBGA- ** Pin AL7 (INC) is defined as BUSCHK#. Allows the system to signal an unsuccessful completion of a bus cycle.
  6 KB (935 words) - 09:30, 27 July 2020
• amd/packages/socket fm1
  !Signal!!Description |CLKIN_H/L||Differential PLL Reference Clock
  7 KB (1,063 words) - 15:50, 4 September 2020
• amd/packages/fp6
  !Signal!!Description |MA/MB_CKE[1:0]||DDR4 DRAM Clock Enable
  20 KB (3,273 words) - 17:47, 10 May 2023
• amd/packages/socket f
  !Signal!!Description |CLKIN_H/L||200-MHz PLL Reference Clock
  11 KB (1,717 words) - 17:25, 5 February 2021
• amd/packages/socket s1g1
  !Signal!!Description |CLKIN_H/L||200 MHz Differential PLL Reference Clock
  8 KB (1,126 words) - 18:53, 12 January 2021
• amd/packages/socket s1g2
  !Signal!!Description |CLKIN_H/L||200 MHz Differential PLL Reference Clock
  8 KB (1,211 words) - 19:08, 12 January 2021
• amd/packages/socket g34
  ...be further unganged into two independent 8-bit links. The package has 1132 signal I/O, 341 power, and 471 ground pins. Package size constrained the HT interf !Signal!!Description
  36 KB (7,214 words) - 15:50, 23 April 2022
• Template:abbr
  -->|rtc=<abbr title="Real Time Clock">{{{1}}}</abbr><!-- -->|ssc=[[wikipedia:Spread spectrum#Clock signal generation|<abbr title="Spread Spectrum Clocking">{{{1}}}</abbr>]]<!--
  13 KB (1,798 words) - 02:43, 17 May 2023
• amd/packages/socket strx4
  ...xtend the Control Fabric to the CCDs, these links run on four data and two clock lanes, as well as USB signals and low speed busses.<!--AMD-55803 PPR SSP-B0 ...nd I/O interfaces on the same pins as {{\\|Socket TR4}} processors and the signal routing on the package differs from {{\\|Socket SP3}} and {{\\|Socket sWRX8
  14 KB (2,188 words) - 11:45, 6 April 2024
• amd/packages/socket sp5
  !Signal!!Type!!Description ...H/L<br/>MA1-ML1_CLK_H/L||O-IOMEM-D||DRAM Channel A-L DIMM 0/1 Differential Clock
  105 KB (21,123 words) - 02:59, 13 March 2023
• amd/packages/socket am5
  !Signal!!Description ...1/MBB1_CLK_H/L[1:0]||DRAM Channel A/B DIMM 0/1 Subchannel A/B Differential Clock
  19 KB (3,162 words) - 17:35, 11 May 2023

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