• intel/microarchitectures/merced
  ** REN: Register remapping ** REG: Register file read
  7 KB (978 words) - 21:16, 20 January 2021
• macro-operation fusion
  ...h fewer bits, free up execution units, tracking information (e.g. in the [[register renaming|rename unit]]), save pipeline bandwidth in all stages from decode [[File:core mopf off.png|350px]]
  11 KB (1,614 words) - 23:01, 8 May 2020
• dec/microarchitectures/alpha 21064
  *** 32-entry integer register file *** 32-entry FP register file
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  * 27-entry register file (from 25) [[File:arm2 block diagram.svg|750px]]
  14 KB (2,093 words) - 04:42, 10 July 2018
• acorn/microarchitectures/arm3
  * <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible) : [[File:arm3 block diagram.svg|600px]]
  7 KB (1,035 words) - 06:24, 21 November 2023
• arm holdings/microarchitectures/arm6
  * <code>MRS</code> - Move from register to CPSR/SPSR * <code>MSR</code> - Move from CPSR/SPSR to register
  11 KB (1,679 words) - 21:00, 15 May 2024
• x86/avx-512
  ...nd 64-bit lane for instance refers to bits 64 ... 95 and 96 ... 127 of the register, again counting from the least significant bit. ...tor registers. Accordingly in assembler code the vector size is implied by register names XMM, YMM, and ZMM. AVX-512 instructions can of course access 32 of al
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/frequency behavior
  .... This table is stored within the read-only processor {{x86|model specific register}} (MSR) and is used to ensure that frequencies do not exceed the lower or u [[File:mixed avx-normal workloads with avx512.png|thumb|right|200px|Cores are grou
  5 KB (797 words) - 01:10, 1 June 2020
• intel/microarchitectures/skylake (server)
  [[File:xeon scalable family decode.png|thumb|right|250px|New Xeon branding]] | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || s
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || | rowspan="2" | [[File:intel pentium silver logo (2017).png|50px|link=intel/pentium_silver]] || ro
  9 KB (1,128 words) - 13:28, 17 July 2023
• register
  {{title|Register}} '''Register''' may refer to:
  390 bytes (39 words) - 03:02, 12 December 2017
• pezy/pezy-scx
  [[File:pezy-sc pe.svg|right|200px]] ...s multithreading]]. A processing element supports 8-way SMT with dedicated register files for each thread. Threads are are interleaved each cycle with switchin
  6 KB (838 words) - 09:33, 9 May 2019
• intel/microarchitectures/cascade lake
  [[File:cascade lake chip.JPG|right|thumb|Cascade Lake]] | [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align
  32 KB (4,535 words) - 05:44, 9 October 2022
• risc-v/registers
  ...t it does suggest that the standard software calling convention should use register <code>x1</code> to store the return address on a call. :[[File:risc-v base integer regsiters.svg|500px]]
  3 KB (424 words) - 09:03, 1 March 2022
• samsung/microarchitectures/m1
  [[File:mongoose 1 soc block diagram.svg|500px]] [[File:mongoose 1 block diagram.svg|900px]]
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger Integer physical register file *** Larger FP physical register
  20 KB (3,149 words) - 10:44, 15 February 2020
• movidius/microarchitectures/shave v2.0
  [[File:shave v2 soc block.svg|800px]] [[File:shave v2 block diagram.svg|900px]]
  12 KB (1,749 words) - 19:05, 20 January 2021
• intel/microarchitectures/polaris
  <!--[[File:intel polaris idf announcement.webm|right]]-->Intel originally announced an :[[File:intel many-core timeline.png|700px]]
  16 KB (2,552 words) - 23:22, 17 May 2019
• amd/microarchitectures/zen 4
  [[File:next-horizon-zen3-4-roadmap.png|right|thumb|400px|Zen 4 on the roadmap.]] * Improved cache load, write and prefetch from/to register (less latency)
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm holdings/microarchitectures/cortex-a76
  [[File:arm deimos roadmap.png|right|thumb|Cortex-A76 and future cores roadmap.]] :[[File:cortex-a76 soc block diagram.svg|550px]]
  14 KB (2,183 words) - 17:15, 17 October 2020

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