Page title matches

Page text matches

• renesas/r-car/h3
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (571 words) - 15:43, 29 December 2018
• renesas/r-car/h3 (sip)
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (495 words) - 16:32, 13 December 2017
• hisilicon/k3/k3v2
  |designer 2=ARM Holdings |isa family=ARM
  3 KB (467 words) - 04:41, 21 July 2018
• hisilicon/k3/k3v2e
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (334 words) - 16:13, 13 December 2017
• hisilicon/kirin
  | developer 2 = ARM Holdings | arch = Performance mobile ARM SOCs
  3 KB (316 words) - 06:18, 3 October 2023
• hisilicon/kirin/970
  |designer 2=ARM Holdings |isa family=ARM
  6 KB (824 words) - 17:25, 1 January 2022
• mediatek/helio/mt6763t
  |designer 2=ARM Holdings |isa family=ARM
  4 KB (534 words) - 05:37, 26 May 2023
• mediatek/helio/p30
  |designer 2=ARM Holdings |isa family=ARM
  2 KB (307 words) - 06:55, 26 June 2019
• 2018
  * February 5: [[Ampere Computing]] announces their first ARM processor, the {{ampere|A1}}. * February 13: [[ARM Holdings|ARM]] announces two new [[neural processors]] IPs - the {{armh|ML processor}} f
  5 KB (639 words) - 01:27, 30 December 2019
• samsung/exynos/9810
  |designer 2=ARM Holdings |isa family=ARM
  5 KB (622 words) - 10:43, 7 March 2024
• cve/cve-2017-5753
  ...gs|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
  12 KB (1,869 words) - 10:01, 27 February 2019
• cve/cve-2017-5715
  ...gs|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
  7 KB (943 words) - 09:59, 27 February 2019
• cve/cve-2017-5754
  ...gs|ARM]] || {{armh|Cortex-A15|l=arch}} || rowspan="4" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
  5 KB (649 words) - 21:16, 8 October 2018
• samsung/exynos/8890
  |isa family=ARM | designer = ARM Holdings
  6 KB (800 words) - 05:21, 25 January 2022
• samsung/coherent interconnect
  ...provides cache coherency and management between the generic [[ARM Holdings|ARM]] {{armh|Cortex-A53|l=arch}} core cluster and Samsung's custom high-perform
  563 bytes (71 words) - 01:43, 5 February 2018
• samsung/exynos/8895
  |designer 2=ARM Holdings |isa family=ARM
  5 KB (713 words) - 07:19, 16 May 2024
• samsung/exynos/3470
  |designer 2=ARM Holdings |isa family=ARM
  443 bytes (55 words) - 22:19, 29 March 2018
• samsung/exynos/4210
  |designer 2=ARM Holdings |isa family=ARM
  449 bytes (55 words) - 00:11, 28 March 2018
• samsung/exynos/4212
  |designer 2=ARM Holdings |isa family=ARM
  457 bytes (54 words) - 00:12, 28 March 2018
• samsung/exynos/4412
  |designer 2=ARM Holdings |isa family=ARM
  439 bytes (55 words) - 08:43, 2 August 2018

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