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• amd/packages/socket s1g2
  ...eration 3.0 and separate power planes for each core and the northbridge, a power saving feature. S1g2 processors support dual plane platforms supplying the * Power Management
  8 KB (1,211 words) - 19:08, 12 January 2021
• amd/packages/socket s1g3
  * Power Management ** Separate core and northbridge power planes
  5 KB (767 words) - 19:14, 12 January 2021
• amd/packages/socket s1g4
  ...r, voltage regulators were integrated on the chip and support for two core power planes was dropped. * Power Management
  10 KB (1,781 words) - 19:23, 12 January 2021
• amd/packages/socket c32
  * Power Management ** Multiple low-power states
  7 KB (998 words) - 20:07, 7 February 2021
• amd/packages/socket g34
  ...ged into two independent 8-bit links. The package has 1132 signal I/O, 341 power, and 471 ground pins. Package size constrained the HT interface to 64 lanes * Power Management
  36 KB (7,214 words) - 15:50, 23 April 2022
• amd/cores/cezanne
  It should be noted that the Ryzen 5000 series also includes low-power mobile APUs developed under the codename "{{\\|Lucienne}}"; the [[amd/ryzen * Thermal Design Power (TDP):
  7 KB (1,000 words) - 14:34, 17 March 2023
• amd/ryzen threadripper/pro 3945wx
  ...ite techdoc|title=AMD Family 17h Models 30h-3Fh sWRX8 Processors Power and Thermal Data Sheet|publ=AMD|pid=56447|rev=1.01|date=2020-08}}
  5 KB (735 words) - 12:48, 18 March 2023
• amd/ryzen threadripper/pro 3955wx
  ...ite techdoc|title=AMD Family 17h Models 30h-3Fh sWRX8 Processors Power and Thermal Data Sheet|publ=AMD|pid=56447|rev=1.01|date=2020-08}}
  5 KB (739 words) - 12:48, 18 March 2023
• amd/ryzen threadripper/pro 3975wx
  ...ite techdoc|title=AMD Family 17h Models 30h-3Fh sWRX8 Processors Power and Thermal Data Sheet|publ=AMD|pid=56447|rev=1.01|date=2020-08}}
  5 KB (739 words) - 12:48, 18 March 2023
• amd/ryzen threadripper/pro 3995wx
  ...ite techdoc|title=AMD Family 17h Models 30h-3Fh sWRX8 Processors Power and Thermal Data Sheet|publ=AMD|pid=56447|rev=1.01|date=2020-08}}
  5 KB (736 words) - 12:48, 18 March 2023
• amd/packages/socket sp5
  ...he {{abbr|PSP}}, SMUs and other IPs, primarily for temperature monitoring, power and frequency control. Physically they use the PCIe Gen 3 protocol. :** 16 lanes, up to 9 ports per group configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x8 + 1x4 + 4x1)
  105 KB (21,123 words) - 02:59, 13 March 2023
• amd/packages/socket am5
  ...ed by pin [[#AM5R1|AM5R1]] and Socket AM5 motherboards are not supposed to power up the socket if an incompatible processor is installed.<!--AMD-57012 Sec 1 |DP0_DIGON||Display Panel Power Enable
  19 KB (3,162 words) - 17:35, 11 May 2023
• intel/microarchitectures/raptor lake
  | {{intel|Raptor Lake U|l=core}} || RPL-U || Ultra-low Power || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room ...} !! rowspan="2" | {{intel|Turbo Boost Max|TBMT}} !! rowspan="2" | {{intel|Thermal Velocity Boost|TVB}}
  9 KB (1,220 words) - 00:23, 17 January 2023
• intel/core i9/i9-13900k
  ...p to 4.3 GHz. This processor has a base power of 125 W and a maximum turbo power of 253 W. This chip supports up to 128 GiB of dual-channel DDR5-5600 ECC me
  6 KB (929 words) - 01:17, 3 October 2022
• intel/core i9/i9-13900kf
  ...p to 4.3 GHz. This processor has a base power of 125 W and a maximum turbo power of 253 W. This chip supports up to 128 GiB of dual-channel DDR5-5600 memory
  5 KB (802 words) - 21:48, 16 December 2022

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