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Core i5-1035G4
General Info
Designer	Intel
Manufacturer	Intel
Model Number	i5-1035G4
Market	Mobile
Introduction	August 1, 2019 (announced) August 1, 2019 (launched)
Release Price	$320.00 (tray)
Shop	Amazon
General Specs
Family	Core i5
Series	i7-10000
Locked	Yes
Frequency	1,100 MHz
Turbo Frequency	3,700 MHz (1 core), 3,300 MHz (4 cores)
Bus type	OPI
Bus rate	4 × 4 GT/s
Clock multiplier	11
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Ice Lake (Client)
Platform	Ice Lake
Core Name	Ice Lake U
Core Family	6
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	4
Threads	8
Max Memory	64 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	15 W
Packaging
Package	FCBGA-1510 (BGA)
Contacts	1510

Core i5-1035G4 is a 64-bit quad-core mid-range performance x86 mobile microprocessor introduced by Intel in mid-2019. This processor, which is based on the Ice Lake microarchitecture, is manufactured on Intel's 2nd generation enhanced 10nm+ process. The i5-1035G4 operates at 1.1 GHz with a TDP of 15 W and Turbo Boost frequency of up to 3.7 GHz. This chip supports up to 64 GiB of quad-channel LPDDR4X-3733 memory and incorporates Intel's GPU with a burst frequency of 1.05 GHz.

This model supports a configurable TDP of TDP-up of 25 W.

Cache

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 320 KiB 327,680 B 0.313 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 192 KiB 196,608 B 0.188 MiB 4x48 KiB 12-way set associative write-back L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     4x512 KiB 8-way set associative write-back L3$ 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB     4x1.5 MiB 12-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3733, DDR4-3200 Supports ECC No Max Mem 64 GiB Controllers 1 Channels 4 Width 32 bit Max Bandwidth 55.63 GiB/s 56,965.12 MiB/s 59.732 GB/s 59,732.258 MB/s 0.0543 TiB/s 0.0597 TB/s Bandwidth Single 13.91 GiB/s Double 27.82 GiB/s Quad 55.63 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
USB Revision: USB 3.2 Gen 2x1 Max Ports: 4 Rate: 10 Gb/s

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU Iris Plus Graphics Designer Intel Device ID 0x8A5A Execution Units 64 Max Displays 3 Max Memory 64 GiB 65,536 MiB 67,108,864 KiB 68,719,476,736 B Frequency 300 MHz 0.3 GHz 300,000 KHz Burst Frequency 1,050 MHz 1.05 GHz 1,050,000 KHz Output DP, eDP, HDMI, DVI Max Resolution HDMI 4096x2304 @32 Hz DP 5120x3200 @60 Hz eDP 5120x3200 @60 Hz Standards DirectX 12 OpenGL 4.5 OpenCL 2.0 DP 1.2 eDP 1.4 HDMI 1.4a Additional Features Intel Quick Sync Video

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a GFNI SSE Galois Field New Instructions AVX Advanced Vector Extensions AVX+GFNI AVX Galois Field New Instructions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_VNNI AVX-512 Vector Neural Network Instructions AVX512_VPOPCNTDQ AVX-512 Vector Population Count Doubleword and Quadword AVX512F+GFNI AVX-512 Galois Field New Instructions AVX512F+VAES AVX-512 Vector AES Instructions AVX512_VBMI2 AVX-512 Vector Bit Manipulation Instructions 2 AVX512_BITALG AVX-512 Bit Algorithms AVX512F+VPCLMULQDQ Vector Carry-Less Multiplication of Quadwords ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions SGX Software Guard Extensions Secure Key Secure Key Technology SMEP OS Guard Technology Flex Memory Flex Memory Access

Die

Main article: Ice Lake SoC Die