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Core i5-1030G7 - Intel
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Core i5-1030G7
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package, front
General Info
DesignerIntel
ManufacturerIntel
Model Numberi5-1030G7
MarketMobile
IntroductionAugust 1, 2019 (announced)
August 1, 2019 (launched)
ShopAmazon
General Specs
FamilyCore i5
Seriesi5-10000
LockedYes
Frequency800 MHz
Turbo Frequency3,500 MHz (1 core),
3,200 MHz (4 cores)
Bus typeOPI
Bus rate4 × 4 GT/s
Clock multiplier8
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureIce Lake
PlatformIce Lake
Core NameIce Lake Y
Core Family6
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP9 W
cTDP up12 W
cTDP up frequency1,100 MHz
Tjunction0 °C – 100 °C
Packaging
PackageFCBGA-1377 (BGA)
Dimension26.5 mm × 18.5 mm × 1.0 mm
Pitch0.43 mm
Contacts1377
SocketType 3
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Core i5-1030G7 is a 64-bit quad-core high-end performance ultra-low power x86 mobile microprocessor introduced by Intel in mid-2019. This chip, which is based on the Ice Lake microarchitecture, is fabricated on Intel's 10 nm process. The i5-1030G7 operates at 800 MHz with a TDP of 9 W supporting a Turbo Boost frequency of up to 3.5 GHz. The processor supports up to 32 GiB of quad-channel LPDDR4X-3733 memory and incorporates Intel's Iris Plus Graphics IGP operating at 300 MHz with a burst frequency of 1.05 GHz.

Cache

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$320 KiB
327,680 B
0.313 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
4x48 KiB12-way set associativewrite-back

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB8-way set associativewrite-back

L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB12-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeLPDDR4X-3733, DDR4-3200
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels4
Width32 bit
Max Bandwidth55.63 GiB/s
56,965.12 MiB/s
59.732 GB/s
59,732.258 MB/s
0.0543 TiB/s
0.0597 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.82 GiB/s
Quad 55.63 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
USBRevision: USB 3.2 Gen 2x1
Max Ports: 4
Rate: 10 Gb/s


Graphics

[Edit/Modify IGP Info]

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Integrated Graphics Information
GPUUHD Graphics
DesignerIntelDevice ID0x8A58
Execution Units64Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency1,050 MHz
1.05 GHz
1,050,000 KHz
OutputDP, eDP, HDMI, DVI

Max Resolution
HDMI4096x2304 @32 Hz
DP5120x3200 @60 Hz
eDP5120x3200 @60 Hz

Standards
DirectX12
OpenGL4.5
OpenCL2.0
DP1.2
eDP1.4
HDMI1.4a

Additional Features
Intel Quick Sync Video

Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
GFNISSE Galois Field New Instructions
AVXAdvanced Vector Extensions
AVX+GFNIAVX Galois Field New Instructions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
AVX512_VPOPCNTDQAVX-512 Vector Population Count Doubleword and Quadword
AVX512F+GFNIAVX-512 Galois Field New Instructions
AVX512F+VAESAVX-512 Vector AES Instructions
AVX512_VBMI2AVX-512 Vector Bit Manipulation Instructions 2
AVX512_BITALGAVX-512 Bit Algorithms
AVX512F+VPCLMULQDQVector Carry-Less Multiplication of Quadwords
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
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