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Process Technology - Intel
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Revision as of 04:46, 11 May 2017 by David (talk | contribs)

This article details Intel's Semiconductor Process Technology.

Timeline

1 µm vs 500 nm yield
Ramps from 1 µm to 65 nm
SRAM test chips from 130 nm to 45 nm
YearProcessNodeMLayersµarchsTransistorAttributes
CHMOS I 3 µm 1 Tox70 nmGate Dielectric
Vdd5 VSRAM1120 µm²
Lg3.0 µm
CPP7 µmMMP11 µm
CHMOS II 2 µm 1 Tox40 nmGate Dielectric
Vdd5 VSRAM (HD)1740 µm²
Lg2.0 µm
CPP5.6 µmMMP8 µm
1982 P646 (CHMOS III) 1.5 µm 1 80286,
80386
Tox25 nmGate DielectricSi2N2O
Vdd5 VSRAM (HD)951.7 µm²
Lg1.5 µm
CPP4.0 µmMMP6.4 µm
1987 P648 1.0 µm 2 80486 Lg1,000 nm
Tox? nmGate Dielectric
Vdd? V
1989 P650 0.8 µm 3 80486 Lg800 nm
Tox? nmGate Dielectric
Vdd? V
1993 P852 0.5 µm 4 P5 Lg500 nm
Tox8.0 nmGate Dielectric
Vdd3.3 V
1995 P854 0.35 µm 4 P6 Lg350 nm
Tox5.2 nmGate Dielectric
Vdd2.5 V
1997 P856
P856.5
0.25 µm 5 P6 Lg200 nm
Tox3.1 nmGate DielectricSiO2
Vdd1.8 V
1999 P858 0.18 µm 6 NetBurst Lg130 nm
Tox2.0 nmGate DielectricSiO2
Vdd1.6 V
2001 P860 0.13 µm 6 Pentium M Lg70 nm
Tox1.4 nmGate DielectricSiO2
Vdd1.4 V
SRAM (HD)2.45 µm²
2003 P1262 90 nm 7 Pentium M intel 90nm gate.png Lg50 nm
Tox1.2 nmGate DielectricSiO2
Vdd1.2 V
SRAM (HD)1.00 µm²
2005 P1264 65 nm 8 Core,
Modified Pentium M
ToxGate DielectricSiO2
VddSRAM0.570 µm²
Lg35 nm
CPP220 nmMMP210 nm
2007 P1266 45 nm 9 Penryn,
Nehalem
ToxGate DielectricHigh-κ
VddSRAM0.346 µm²
Lg25 nm
CPP160 nmMMP180 nm
2009 P1268 32 nm 10 Westmere,
Sandy Bridge
ToxGate DielectricHigh-κ
VddSRAM0.148 µm²
Lg30 nm
CPP112.5 nmMMP112.5 nm
2011 P1270 22 nm 11 Ivy Bridge,
Haswell
ToxGate DielectricHigh-κ
VddSRAM0.092 µm²
Lg26 nm
CPP90 nmMMP80 nm
2014 P1272 14 nm 11 Broadwell,
Skylake,
Kaby Lake,
Coffee Lake
ToxGate DielectricHigh-κ
VddSRAM0.0499 µm²
Lg20 nm
CPP70 nmMMP52 nm
2017 P1274 10 nm Cannonlake,
Icelake,
Tigerlake
ToxGate DielectricHigh-κ
VddSRAM0.0312 µm²
Lg18 nm ?
CPP54 nmMMP36 nm
2019 P1276 7 nm
2022 P1278 5 nm