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Revision as of 13:54, 14 January 2019
Edit Values | |
Exynos 9820 | |
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General Info | |
Designer | Samsung, ARM Holdings |
Manufacturer | Samsung |
Model Number | 9820 |
Market | Mobile |
Introduction | November 14, 2018 (announced) January, 2019 (launched) |
General Specs | |
Family | Exynos |
Series | Exynos 9 |
Microarchitecture | |
ISA | ARMv8.2 (ARM) |
Microarchitecture | Mongoose 4, Cortex-A75, Cortex-A55 |
Core Name | Mongoose 4, Cortex-A75, Cortex-A55 |
Process | 8 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 12 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Succession | |
Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2019. The processor is fabricated on Samsung's 8nm LPP (Low Power Plus) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 4 big cores and 2 Cortex-A75 middle cores and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.
Contents
Cache
- Main articles: Mongoose § Cache and Cortex-A76 § Cache
For the Mongoose 4 core cluster:
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A75 cluster:
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A55 cluster:
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Codec | Encode | Decode |
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HEVC (H.265) | ✔ | ✔ |
MPEG-4 AVC (H.264) | ✔ | ✔ |
VP9 | ✔ | ✔ |
All at 4K UHD 150fps.
Wireless
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Cellular | |||||||
4G |
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ISP
- 24MP Rear
- 24MP Front
- 16MP+16MP Dual
Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Utilizing devices
- Samsung Galaxy S10
This list is incomplete; you can help by expanding it.
Documents
- all microprocessor models
- microprocessor models by samsung
- microprocessor models by samsung based on mongoose 4
- microprocessor models by samsung based on cortex-a75
- microprocessor models by samsung based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on mongoose 4
- microprocessor models by arm holdings based on cortex-a75
- microprocessor models by arm holdings based on cortex-a55
- microprocessor models require attention
core count | 8 + |
core name | Cheetah +, Cortex-A75 + and Cortex-A55 + |
designer | Samsung + and ARM Holdings + |
die area | 127 mm² (0.197 in², 1.27 cm², 127,000,000 µm²) + |
family | Exynos + |
first announced | November 14, 2018 + |
first launched | January 2019 + |
full page name | samsung/exynos/9820 + |
has 4g support | true + |
has ecc memory support | false + |
has lte advanced support | true + |
instance of | microprocessor + |
integrated gpu | Mali-G76 + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 702 MHz (0.702 GHz, 702,000 KHz) + |
isa | ARMv8.2 + |
isa family | ARM + |
l1$ size | 192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + and 16-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + and 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | January 2019 + |
main image | ![]() |
manufacturer | Samsung + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 12,288 MiB (12,582,912 KiB, 12,884,901,888 B, 12 GiB, 0.0117 TiB) + |
max memory bandwidth | 26.82 GiB/s (27,463.68 MiB/s, 28.798 GB/s, 28,797.756 MB/s, 0.0262 TiB/s, 0.0288 TB/s) + |
max memory channels | 4 + |
microarchitecture | Exynos M4 +, Cortex-A75 + and Cortex-A55 + |
model number | 9820 + |
name | Exynos 9820 + |
process | 8 nm (0.008 μm, 8.0e-6 mm) + |
series | Exynos 9 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3600 + |
technology | CMOS + |
thread count | 8 + |
used by | Samsung Galaxy S10 +, Samsung Galaxy S10 5G +, Samsung Galaxy S10+ + and Samsung Galaxy S10e + |
user equipment category downlink | 20 + |
user equipment category uplink | 20 + |
word size | 64 bit (8 octets, 16 nibbles) + |