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Difference between revisions of "arm holdings/microarchitectures/cortex-a7"
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== Die == | == Die == | ||
=== MediaTek [[MT6595]] === | === MediaTek [[MT6595]] === | ||
− | |||
* TSMC [[28 nm process]] | * TSMC [[28 nm process]] | ||
* 89 mm² die size | * 89 mm² die size |
Revision as of 13:43, 29 December 2018
Edit Values | |
Cortex-A7 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | October 19, 2011 |
Process | 40 nm, 28 nm |
Succession | |
Cortex-A7 (codename Kingfisher) is the successor to the Cortex-A9, a high efficiency ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A7 was introduced along with the big.LITTLE technology so that it could be integrated along with the a higher-performance core such as the Cortex-A15 or the Cortex-A17 for better energy and power efficiency.
Contents
Architecture
Key changes from Cortex-A9
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Block Diagram
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Memory Hierarchy
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Die
MediaTek MT6595
- TSMC 28 nm process
- 89 mm² die size
- Quad-core Cortex-A7
- ~0.48 mm² per core
- Quad-core Cortex-A17 + 2 MiB L2
- ~1.93 mm² per core
- ~3.93 mm² for 2 MiB L2
(small quad-core is unlabeled below the big core cluster)
Facts about "Cortex-A7 - Microarchitectures - ARM"
codename | Cortex-A7 + |
designer | ARM Holdings + |
first launched | October 19, 2011 + |
full page name | arm holdings/microarchitectures/cortex-a7 + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A7 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) + |