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Difference between revisions of "movidius/microarchitectures/shave v3.0"
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'''Fragrak''' or '''Streaming Hybrid Architecture Vector Engine v3.0''' ('''SHAVE v3.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors, serving as a successor to the {{\\|SHAVE v2.0}}. SHAVE-based products are branded as the {{movidius|Myriad|Myriad 2}} family of vision processors. | '''Fragrak''' or '''Streaming Hybrid Architecture Vector Engine v3.0''' ('''SHAVE v3.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors, serving as a successor to the {{\\|SHAVE v2.0}}. SHAVE-based products are branded as the {{movidius|Myriad|Myriad 2}} family of vision processors. | ||
| + | |||
| + | == Process Technology == | ||
| + | {{main|28 nm lithography process}} | ||
| + | This microarchitecture was designed for [[TSMC]]'s [[28 nm process]]. | ||
| + | |||
| + | == Architecture == | ||
| + | |||
| + | === Key changes from {{\\|SHAVE v2.0}} === | ||
| + | * [[28 nm process]] (from [[65 nm]]) | ||
| + | * [[LEON4]] [[SPARC]] core (from [[LEON3]]) | ||
| + | * Added support for [[OpenCL]] | ||
| + | * 12 SHAVE cores (from 8) | ||
Revision as of 21:57, 12 March 2018
| Edit Values | |
| SHAVE v3.0 µarch | |
| General Info | |
| Arch Type | Accelerator |
| Designer | Movidius |
| Manufacturer | TSMC |
| Introduction | 2014 |
| Process | 28 nm |
| Pipeline | |
| Type | VLLIW |
| Instructions | |
| ISA | SHAVE, SPARC v8 |
| Cache | |
| L2 Cache | 256 KiB/chip 2-way set associative |
| Side Cache | 128-256 MiB SDRAM/chip |
| Succession | |
Fragrak or Streaming Hybrid Architecture Vector Engine v3.0 (SHAVE v3.0) is an accelerator microarchitecture designed by Movidius for their vision processors, serving as a successor to the SHAVE v2.0. SHAVE-based products are branded as the Myriad 2 family of vision processors.
Process Technology
- Main article: 28 nm lithography process
This microarchitecture was designed for TSMC's 28 nm process.
Architecture
Key changes from SHAVE v2.0
| codename | SHAVE v3.0 + |
| designer | Movidius + |
| first launched | 2014 + |
| full page name | movidius/microarchitectures/shave v3.0 + |
| instance of | microarchitecture + |
| instruction set architecture | SHAVE + and SPARC v8 + |
| manufacturer | TSMC + |
| name | SHAVE v3.0 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |