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Difference between revisions of "samsung/exynos/9810"
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'''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a {{armh|DynamiQ}} configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} cores operating at 2.9 GHz and 4 {{armh|Cortex-A55|l=arch}} cores operating at 1.9 GHz. The chip incorporates a {{armh|Mali G72|Mali G72}} (MP18) GPU and a 1.2 Gbps [[LTE]] modem. | '''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a {{armh|DynamiQ}} configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} cores operating at 2.9 GHz and 4 {{armh|Cortex-A55|l=arch}} cores operating at 1.9 GHz. The chip incorporates a {{armh|Mali G72|Mali G72}} (MP18) GPU and a 1.2 Gbps [[LTE]] modem. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|samsung/microarchitectures/mongoose_3#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Mongoose 3 § Cache||l2=Cortex-A55 § Cache}} | ||
+ | For the {{samsung|Mongoose 3|l=arch}} core cluster: | ||
+ | {{cache size}} | ||
+ | |||
+ | For the {{armh|Cortex-A55|l=arch}} cluster: | ||
+ | |||
+ | {{cache size | ||
+ | |l1 cache=256 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=2-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=4-way set associative | ||
+ | |l2 cache=256 KiB | ||
+ | |l2 break=1x256 KiB | ||
+ | |l2 desc=16-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=LPDDR4-3600 | ||
+ | |ecc=No | ||
+ | |max mem=4 GiB | ||
+ | |controllers=2 | ||
+ | |channels=2 | ||
+ | |width=32 bit | ||
+ | |frequency=1800 MHz | ||
+ | |bandwidth schan=13.41 GiB/s | ||
+ | |bandwidth dchan=26.82 GiB/s | ||
+ | }} |
Revision as of 16:13, 25 February 2018
Edit Values | |
Exynos 9810 | |
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General Info | |
Designer | Samsung, ARM Holdings |
Manufacturer | Samsung |
Model Number | 9810 |
Market | Mobile |
Introduction | January 3, 2018 (announced) |
General Specs | |
Family | Exynos |
Series | 9000 |
Frequency | 2,900 MHz, 1,900 MHz |
Microarchitecture | |
ISA | ARMv8.3 (ARM) |
Microarchitecture | Mongoose M3, Cortex-A55 |
Core Name | Mongoose M3, Cortex-A55 |
Process | 10 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a DynamiQ configuration consisting of 4 Mongoose 3 cores operating at 2.9 GHz and 4 Cortex-A55 cores operating at 1.9 GHz. The chip incorporates a Mali G72 (MP18) GPU and a 1.2 Gbps LTE modem.
Cache
- Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache
For the Mongoose 3 core cluster:
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A55 cluster:
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Categories:
- all microprocessor models
- microprocessor models by samsung
- microprocessor models by samsung based on mongoose m3
- microprocessor models by samsung based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on mongoose m3
- microprocessor models by arm holdings based on cortex-a55
- future microprocessor models
Facts about "Exynos 9810 - Samsung"
base frequency | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + and 1,900 MHz (1.9 GHz, 1,900,000 kHz) + |
core count | 8 + |
core name | Mongoose M3 + and Cortex-A55 + |
designer | Samsung + and ARM Holdings + |
family | Exynos + |
first announced | January 3, 2018 + |
full page name | samsung/exynos/9810 + |
has ecc memory support | false + |
instance of | microprocessor + |
isa | ARMv8.3 + |
isa family | ARM + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
ldate | 3000 + |
main image | ![]() |
manufacturer | Samsung + |
market segment | Mobile + |
max cpu count | 1 + |
max memory channels | 2 + |
microarchitecture | Mongoose M3 + and Cortex-A55 + |
model number | 9810 + |
name | Exynos 9810 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
series | 9000 + |
smp max ways | 1 + |
supported memory type | LPDDR4-3600 + |
technology | CMOS + |
thread count | 8 + |
word size | 64 bit (8 octets, 16 nibbles) + |