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'''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a {{armh|DynamiQ}} configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} cores operating at 2.9 GHz and 4 {{armh|Cortex-A55|l=arch}} cores operating at 1.9 GHz. The chip incorporates a {{armh|Mali G72|Mali G72}} (MP18) GPU and a 1.2 Gbps [[LTE]] modem.
 
'''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a {{armh|DynamiQ}} configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} cores operating at 2.9 GHz and 4 {{armh|Cortex-A55|l=arch}} cores operating at 1.9 GHz. The chip incorporates a {{armh|Mali G72|Mali G72}} (MP18) GPU and a 1.2 Gbps [[LTE]] modem.
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== Cache ==
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{{main|samsung/microarchitectures/mongoose_3#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Mongoose 3 § Cache||l2=Cortex-A55 § Cache}}
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For the {{samsung|Mongoose 3|l=arch}} core cluster:
 +
{{cache size}}
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For the {{armh|Cortex-A55|l=arch}} cluster:
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 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=256 KiB
 +
|l2 break=1x256 KiB
 +
|l2 desc=16-way set associative
 +
}}
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 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4-3600
 +
|ecc=No
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|max mem=4 GiB
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|controllers=2
 +
|channels=2
 +
|width=32 bit
 +
|frequency=1800 MHz
 +
|bandwidth schan=13.41 GiB/s
 +
|bandwidth dchan=26.82 GiB/s
 +
}}

Revision as of 15:13, 25 February 2018

Edit Values
Exynos 9810
exynos 9810.png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9810
MarketMobile
IntroductionJanuary 3, 2018 (announced)
General Specs
FamilyExynos
Series9000
Frequency2,900 MHz, 1,900 MHz
Microarchitecture
ISAARMv8.3 (ARM)
MicroarchitectureMongoose M3, Cortex-A55
Core NameMongoose M3, Cortex-A55
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)

Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a DynamiQ configuration consisting of 4 Mongoose 3 cores operating at 2.9 GHz and 4 Cortex-A55 cores operating at 1.9 GHz. The chip incorporates a Mali G72 (MP18) GPU and a 1.2 Gbps LTE modem.

Cache

Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache

For the Mongoose 3 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB2-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-3600
Supports ECCNo
Max Mem4 GiB
Frequency1800 MHz
Controllers2
Channels2
Width32 bit
Bandwidth
Single 13.41 GiB/s
Double 26.82 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/9810&oldid=74519"
Facts about "Exynos 9810 - Samsung"
RDF feed
base frequency2,900 MHz (2.9 GHz, 2,900,000 kHz) + and 1,900 MHz (1.9 GHz, 1,900,000 kHz) +
core count8 +
core nameMongoose M3 + and Cortex-A55 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedJanuary 3, 2018 +
full page namesamsung/exynos/9810 +
has ecc memory supportfalse +
instance ofmicroprocessor +
isaARMv8.3 +
isa familyARM +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description2-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate3000 +
main imageFile:exynos 9810.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory channels2 +
microarchitectureMongoose M3 + and Cortex-A55 +
model number9810 +
nameExynos 9810 +
process10 nm (0.01 μm, 1.0e-5 mm) +
series9000 +
smp max ways1 +
supported memory typeLPDDR4-3600 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +