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Difference between revisions of "zhaoxin/kaixian/kx-5540"
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'''KaiXian KX-5540''' is a {{arch|64}} [[quad-core]] [[x86]] microprocessor designed by [[Zhaoxin]] and introduced in late [[2017]] specifically for the [[Chinese]] market. This processor is fabricated on a [[28 nm process]] based on the {{zhaoxin|WuDaoKou|l=arch}} microarchitecture. The KX-5640 operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-5540 also incorporates an integrated graphics processor.
 
'''KaiXian KX-5540''' is a {{arch|64}} [[quad-core]] [[x86]] microprocessor designed by [[Zhaoxin]] and introduced in late [[2017]] specifically for the [[Chinese]] market. This processor is fabricated on a [[28 nm process]] based on the {{zhaoxin|WuDaoKou|l=arch}} microarchitecture. The KX-5640 operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-5540 also incorporates an integrated graphics processor.
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{{unknown features}}
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== Cache ==
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{{main|zhaoxin/microarchitectures/wudaokou#Memory_Hierarchy|l1=WuDaoKou § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=8-way set associative
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|l2 cache=4 MiB
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|l2 break=1x4 MiB
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|l2 desc=32-way set associative
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}}

Revision as of 19:05, 20 January 2018

Edit Values
KaiXian KX-5540
KX-5540.png
KX-5540 front
General Info
DesignerZhaoxin
ManufacturerHLMC
Model NumberKX-5540
Part NumberKX-5540
MarketDesktop, Mobile, Embedded
IntroductionDecember 28, 2017 (announced)
December 28, 2017 (launched)
General Specs
FamilyKaiXian
SeriesKX-5000
Frequency1,800 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWuDaoKou
Process28 nm
Transistors2,100,000,000
TechnologyCMOS
Die187 mm²
Word Size64 bit
Cores4
Threads4
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Tjunction0 °C – 90 °C

KaiXian KX-5540 is a 64-bit quad-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KX-5640 operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-5540 also incorporates an integrated graphics processor.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB32-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaixian/kx-5540&oldid=72842"
Facts about "KaiXian KX-5540 - Zhaoxin"
RDF feed
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typePCIe 3.0 +
core count4 +
designerZhaoxin +
die area187 mm² (0.29 in², 1.87 cm², 187,000,000 µm²) +
familyKaiXian +
first announcedDecember 28, 2017 +
first launchedDecember 28, 2017 +
full page namezhaoxin/kaixian/kx-5540 +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description32-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateDecember 28, 2017 +
main imageFile:KX-5540.png +
main image captionKX-5540 front +
manufacturerHLMC +
market segmentDesktop +, Mobile + and Embedded +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
microarchitectureWuDaoKou +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberKX-5540 +
nameKaiXian KX-5540 +
part numberKX-5540 +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesKX-5000 +
smp max ways1 +
technologyCMOS +
thread count4 +
transistor count2,100,000,000 +
word size64 bit (8 octets, 16 nibbles) +