Semiconductor & Computer Engineering
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Difference between revisions of "zhaoxin/microarchitectures/wudaokou"
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=== Key changes from {{\\|Zhangjiang}} === | === Key changes from {{\\|Zhangjiang}} === | ||
| + | * 1.4x performance | ||
* [[8 cores]] per die (up from 4) | * [[8 cores]] per die (up from 4) | ||
* SoC design | * SoC design | ||
Revision as of 21:37, 15 January 2018
| Edit Values | |
| WuDaoKou µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Zhaoxin |
| Manufacturer | HLMC |
| Introduction | December 28, 2017 |
| Process | 28 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Succession | |
WuDaoKou is the successor to Zhangjiang, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Contents
Brands
| Family | Series | Description |
|---|---|---|
| KaiXian | KX (5000) | Desktop, Laptops |
| Kaisheng | KH (20000) | Storage, Servers |
Process Technology
WuDaoKou is manufactured on HLMC's 28 nm process.
Architecture
Key changes from Zhangjiang
- 1.4x performance
- 8 cores per die (up from 4)
- SoC design
- New Uncore
- northbridge moved on-die
- PCIe 3.0 (from 2.0)
- DDR4 (From DDR3)
- New integrated graphics processor
- HD Audio Output/Codec
- New Uncore
- Core
- Pipeline was reduced by 5 stages
- Execution engines were re-balanced
- Branch prediction unit was reworked and optimized
- FSB removed
- x4 PCIe 3.0 communication with southbridge chipset
- Chipset
- Gigabit Ethernet port (RGMII)
- USB 3.1 Gen2 (Type-C) ports
- SATA 3.0 ports
This list is incomplete; you can help by expanding it.
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
| |
This section is empty; you can help add the missing info by editing this page. |
Die
- HLMC 28 nm process
- 187 mm² die size
- 2,100,000,000 transistors
Facts about "WuDaoKou - Microarchitectures - Zhaoxin"
| codename | WuDaoKou + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | December 28, 2017 + |
| full page name | zhaoxin/microarchitectures/wudaokou + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | HLMC + |
| microarchitecture type | CPU + |
| name | WuDaoKou + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |