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[[File:intel 90nm 32nm yield.png|300px|thumb|[[90 nm]] to [[32 nm]]]]
 
[[File:intel 90nm 32nm yield.png|300px|thumb|[[90 nm]] to [[32 nm]]]]
 
[[File:intel scaling from 45nm to 10nm.png|300px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
 
[[File:intel scaling from 45nm to 10nm.png|300px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
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<div style="overflow-x: scroll; white-space: nowrap;">
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<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px">
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<table class="wikitable" style="text-align: center;">
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<table class="wikitable" style="text-align: center; ">
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
 
{{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
 
{{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
 
   |archs=8085, 8086, 8088, 80186
 
   |archs=8085, 8086, 8088, 80186
−
   |a1=T<sub>ox</sub> |d1=70 nm    |a12=Gate Dielectric |d12=
+
   |a1=T<sub>ox</sub> |d1=70 nm    |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22= 1120 µm²
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22= 1120 µm²
 
   |a3=L<sub>g</sub>  |d3=3.0 µm
 
   |a3=L<sub>g</sub>  |d3=3.0 µm
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{{intel proc tech |year=1979 |name=CHMOS II |mlayers=1 |node=2 µm
 
{{intel proc tech |year=1979 |name=CHMOS II |mlayers=1 |node=2 µm
 
   |archs=
 
   |archs=
−
   |a1=T<sub>ox</sub> |d1=40 nm    |a12=Gate Dielectric |d12=
+
   |a1=T<sub>ox</sub> |d1=40 nm    |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=1740 µm²
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=1740 µm²
 
   |a3=L<sub>g</sub>  |d3=2.0 µm
 
   |a3=L<sub>g</sub>  |d3=2.0 µm
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{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm
 
{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm
 
   |archs=80286, 80386
 
   |archs=80286, 80386
−
   |a1=T<sub>ox</sub> |d1=25 nm    |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O
+
   |a1=T<sub>ox</sub> |d1=25 nm    |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=951.7 µm²
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=951.7 µm²
 
   |a3=L<sub>g</sub>  |d3=1.5 µm
 
   |a3=L<sub>g</sub>  |d3=1.5 µm
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{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
 
{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
 
   |archs=80486
 
   |archs=80486
−
   |a1=T<sub>ox</sub> |d1=          |a12=Gate Dielectric |d12=
+
   |a1=T<sub>ox</sub> |d1=          |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=220 µm²
 
   |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22=220 µm²
 
   |a3=L<sub>g</sub>  |d3=1.0 µm
 
   |a3=L<sub>g</sub>  |d3=1.0 µm
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{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
 
{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
 
   |archs=80486
 
   |archs=80486
−
   |a1=T<sub>ox</sub> |d1=15 nm    |a12=Gate Dielectric |d12=
+
   |a1=T<sub>ox</sub> |d1=15 nm    |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=4 V      |a22=SRAM            |d22=111 µm²
 
   |a2=V<sub>dd</sub> |d2=4 V      |a22=SRAM            |d22=111 µm²
 
   |a3=L<sub>g</sub>  |d3=800 µm
 
   |a3=L<sub>g</sub>  |d3=800 µm
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{{intel proc tech |year=1991 |name=P652 |mlayers=4 |node=0.6 µm
 
{{intel proc tech |year=1991 |name=P652 |mlayers=4 |node=0.6 µm
 
   |archs=80486, P5
 
   |archs=80486, P5
−
   |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=
+
   |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=SiO<sub>2</sub>
 
   |a2=V<sub>dd</sub> |d2=3.3 V    |a22=SRAM            |d22=
 
   |a2=V<sub>dd</sub> |d2=3.3 V    |a22=SRAM            |d22=
 
   |a3=L<sub>g</sub>  |d3=600 µm
 
   |a3=L<sub>g</sub>  |d3=600 µm
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{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
 
{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
 
   |archs=P5
 
   |archs=P5
−
   |a1=L<sub>g</sub> |d1=500 nm
+
   |a1=T<sub>ox</sub> |d1=8 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
−
   |a2=T<sub>ox</sub> |d2=8.0 nm |a22=Gate Dielectric |d22=44 µm²
+
   |a2=V<sub>dd</sub> |d2=3.3 V      |a22=SRAM            |d22=44 µm²
−
   |a3=V<sub>dd</sub> |d3=3.3 V
+
   |a3=L<sub>g</sub> |d3=500 nm
 +
  |a4=CPP            |d4=          |a42=MMP            |d42= 
 
}}
 
}}
 
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm
 
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm

Revision as of 17:16, 22 May 2017

This article details details Intel's Semiconductor Process Technology history for research and posterity. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers.

Timeline

1 µm vs 500 nm yield
historical roadmap
Ramps from 1 µm to 65 nm
Roadmap past 180 nm
SRAM test chips from 130 nm to 45 nm
Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.
65 nm to 32 nm SRAM scaling
90 nm to 32 nm
Intel scaling from 45 nm to 10 nm
YearProcessNodeMLayersµarchsGateInterconnectsAttributes
1977 CHMOS I 3 µm 1 8085,
8086,
8088,
80186		 Tox70 nmGate DielectricSiO2
Vdd5 VSRAM1120 µm²
Lg3.0 µm
CPP7 µmMMP11 µm
1979 CHMOS II 2 µm 1 Tox40 nmGate DielectricSiO2
Vdd5 VSRAM1740 µm²
Lg2.0 µm
CPP5.6 µmMMP8 µm
1982 P646
(CHMOS III)		 1.5 µm 1 80286,
80386		 Tox25 nmGate DielectricSiO2
Vdd5 VSRAM951.7 µm²
Lg1.5 µm
CPP4.0 µmMMP6.4 µm
1987 P648 1.0 µm 2 80486 ToxGate DielectricSiO2
Vdd5 VSRAM220 µm²
Lg1.0 µm
CPPMMP
1989 P650 0.8 µm 3 80486 Tox15 nmGate DielectricSiO2
Vdd4 VSRAM111 µm²
Lg800 µm
CPP1.7 µmMMP2 µm
1991 P652 0.6 µm 4 80486,
P5		 Tox8 nmGate DielectricSiO2
Vdd3.3 VSRAM
Lg600 µm
CPPMMP1.4 µm
1993 P852 0.5 µm 4 P5 Tox8 nmGate DielectricSiO2
Vdd3.3 VSRAM44 µm²
Lg500 nm
CPPMMP
1995 P854 0.35 µm 4 P6 Tox6 nmGate DielectricSiO2
Vdd2.5 VSRAM20.5 µm²
Lg350 nm
CPP920 nmMMP880 nm
1997 P856 0.25 µm 5 P6 Tox4.08 nmGate DielectricSiO2
Vdd1.8 VSRAM10.26 µm²
Lg200 nm
CPP500 nmMMP640 nm
1998 P856.5 0.25 µm 5 P6 Tox4.08 nmGate DielectricSiO2
Vdd1.8 VSRAM9.26 µm²
Lg200 nm
CPP475 nmMMP608 nm
1999 P858 0.18 µm 6 NetBurst intel 180nm gate.png Tox2.0 nmGate DielectricSiO2
Vdd1.6 VSRAM5.59 µm²
Lg130 nm
CPP480 nmMMP500 nm
2001 P860 0.13 µm 6 Pentium M intel 130nm gate.png intel 130nm gate interconnect.pngTox1.4 nmGate DielectricSiO2
Vdd1.4 VSRAM2.45 µm²
Lg70 nm
CPP336 nmMMP345 nm
2003 P1262 90 nm 7 Pentium M intel 90nm gate.png intel 90nm gate interconnect.pngTox1.2 nmGate DielectricSiO2
Vdd1.2 VSRAM1.00 µm²
Lg50 nm
CPP260 nmMMP220 nm
2005 P1264 65 nm 8 Core,
Modified Pentium M		 intel 65nm gate.png intel 65nm gate interconnect.pngToxGate DielectricSiO2
VddSRAM0.570 µm²
Lg35 nm
CPP220 nmMMP210 nm
2007 P1266 45 nm 9 Penryn,
Nehalem		 intel 45nm gate.png intel 45nm gate interconnects.pngToxGate DielectricHigh-κ
VddSRAM0.346 µm²
Lg25 nm
CPP160 nmMMP180 nm
2009 P1268 32 nm 10 Westmere,
Sandy Bridge		 intel 32nm gate.png intel 32nm gate interconnect.pngToxGate DielectricHigh-κ
Vdd0.75 VSRAM0.148 µm²
Lg30 nm
CPP112.5 nmMMP112.5 nm
2011 P1270 22 nm 11 Ivy Bridge,
Haswell		 intel 22nm gate.png intel 22nm gate interconnect.pngToxGate DielectricHigh-κ
Vdd0.75 VSRAM0.092 µm²
Lg26 nm
CPP90 nmMMP80 nm
Pfin60 nm
Wfin8 nmHfin34 nm
2014 P1272 14 nm 11 Broadwell,
Skylake,
Kaby Lake,
Coffee Lake		 intel 14nm gate top.png intel 14nm gate interconnect.pngToxGate DielectricHigh-κ
VddSRAM0.0499 µm²
Lg20 nm
CPP70 nmMMP52 nm
Pfin42 nm
Wfin8 nmHfin42 nm
2017 P1274 10 nm Cannonlake,
Icelake,
Tigerlake		 ToxGate DielectricHigh-κ
VddSRAM0.0312 µm²
Lg18 nm ?
CPP54 nmMMP36 nm
Pfin34 nm
Wfin5 nmHfin53 nm
2019 P1276 7 nm
2022 P1278 5 nm

SRAM Scaling

For Intel, from 2 µm to 10 nm, SRAM 6T bit cells have had an average shrink of 0.496x in an attempt to maintain Moore's Law double density observation/requirement. Note that SRAM shrunk more significantly prior to the 65 nm process node.


intel sram bit cell scaling.png

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