Difference between revisions of "intel/process"

Revision as of 04:40, 11 May 2017

This article details Intel's Semiconductor Process Technology.

Timeline

1 µm vs 500 nm yield

Ramps from 1 µm to 65 nm

SRAM test chips from 130 nm to 45 nm

Year	Process	Node	MLayers	µarchs
	CHMOS I	3 µm	1		T_ox	70 nm	Gate Dielectric
					V_dd	5 V	SRAM	1120 µm²
					L_g	3.0 µm
					CPP	7 µm	MMP	11 µm
	CHMOS II	2 µm	1		T_ox	40 nm	Gate Dielectric
					V_dd	5 V	SRAM (HD)	1740 µm²
					L_g	2.0 µm
					CPP	5.6 µm	MMP	8 µm
1982	P646 (CHMOS III)	1.5 µm	1	80286, 80386	T_ox	25 nm	Gate Dielectric	Si₂N₂O
					V_dd	5 V	SRAM (HD)	951.7 µm²
					L_g	1.5 µm
					CPP	4.0 µm	MMP	6.4 µm
1987	P648	1.0 µm	2	80486	L_g	1,000 nm
					T_ox	? nm	Gate Dielectric
					V_dd	? V
1989	P650	0.8 µm	3	80486	L_g	800 nm
					T_ox	? nm	Gate Dielectric
					V_dd	? V
1993	P852	0.5 µm	4	P5	L_g	500 nm
					T_ox	8.0 nm	Gate Dielectric
					V_dd	3.3 V
1995	P854	0.35 µm	4	P6	L_g	350 nm
					T_ox	5.2 nm	Gate Dielectric
					V_dd	2.5 V
1997	P856 P856.5	0.25 µm	5	P6	L_g	200 nm
					T_ox	3.1 nm	Gate Dielectric	SiO₂
					V_dd	1.8 V
1999	P858	0.18 µm	6	NetBurst	L_g	130 nm
					T_ox	2.0 nm	Gate Dielectric	SiO₂
					V_dd	1.6 V
2001	P860	0.13 µm	6	Pentium M	L_g	70 nm
					T_ox	1.4 nm	Gate Dielectric	SiO₂
					V_dd	1.4 V
					SRAM (HD)	2.45 µm²
2003	P1262	90 nm	7	Pentium M	L_g	50 nm
					T_ox	1.2 nm	Gate Dielectric	SiO₂
					V_dd	1.2 V
					SRAM (HD)	1.00 µm²
2005	P1264	65 nm	8	Core, Modified Pentium M	L_g	35 nm
					T_ox	? nm	Gate Dielectric	SiO₂
					V_dd	? V
					SRAM (HD)	0.570 µm²
2007	P1266	45 nm	9	Penryn, Nehalem	L_g	25 nm
					T_ox	? nm	Gate Dielectric	High-κ
					V_dd	? V
					SRAM (HD)	0.346 µm²
2009	P1268	32 nm	10	Westmere, Sandy Bridge	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.092 µm²
					L_g	30 nm
					CPP	112.5 nm	MMP	112.5 nm
2011	P1270	22 nm	11	Ivy Bridge, Haswell	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.092 µm²
					L_g	26 nm
					CPP	90 nm	MMP	80 nm
2014	P1272	14 nm	11	Broadwell, Skylake, Kaby Lake, Coffee Lake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0499 µm²
					L_g	20 nm
					CPP	70 nm	MMP	52 nm
2017	P1274	10 nm		Cannonlake, Icelake, Tigerlake	T_ox		Gate Dielectric	High-κ
					V_dd		SRAM	0.0312 µm²
					L_g	18 nm ?
					CPP	54 nm	MMP	36 nm
2019	P1276	7 nm
2022	P1278	5 nm

@@ Line 3: / Line 3: @@
 == Timeline ==
+[[File:intel 1micron yield.png|right|300px|thumb|[[1 µm]] vs [[500 nm]] yield]]
+[[File:intel tech ramps 1um to 65nm.png|right|300px|thumb|Ramps from [[1 µm]] to [[65 nm]]]]
+[[File:intel sram tests 130nm to 45nm.png|right|300px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]]]
+<div style="overflow-x: scroll; white-space: nowrap;">
 <table class="wikitable" style="text-align: center;">
-<tr><th>Year</th><th>Process Name</th><th>Node Name</th><th>Metal Layers</th><th>µarchs</th><th colspan="4">Attributes</th></tr>
+<tr><th>Year</th><th>Process</th><th>Node</th><th>MLayers</th><th>µarchs</th><th>Transistor</th><th colspan="4">Attributes</th></tr>
-{{intel proc tech |year=1982 |name=P646 |mlayers=2 |node=1.5 µm
+{{intel proc tech |year= |name=CHMOS I |mlayers=1 |node=3 µm
+  |archs=
+  |a1=T<sub>ox</sub> |d1=70 nm     |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22= 1120 µm²
+  |a3=L<sub>g</sub>  |d3=3.0 µm
+  |a4=CPP            |d4=7 µm    |a42=MMP             |d42=11 µm
+}}
+{{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm
+  |archs=
+  |a1=T<sub>ox</sub> |d1=40 nm     |a12=Gate Dielectric |d12=
+  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM (HD)       |d22=1740 µm²
+  |a3=L<sub>g</sub>  |d3=2.0 µm
+  |a4=CPP            |d4=5.6 µm    |a42=MMP             |d42=8 µm
+}}
+{{intel proc tech |year=1982 |name=P646 (CHMOS III) |mlayers=1 |node=1.5 µm
    |archs=80286, 80386
-   |a1=L<sub>g</sub>  |d1=1,500 nm
+   |a1=T<sub>ox</sub> |d1=25 nm     |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O
-  |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=Si<sub>2</sub>N<sub>2</sub>O
+   |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM (HD)       |d22=951.7 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+  |a3=L<sub>g</sub>  |d3=1.5 µm
+  |a4=CPP            |d4=4.0 µm    |a42=MMP             |d42=6.4 µm
 }}
 {{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
@@ Line 52: / Line 71: @@
    |a2=T<sub>ox</sub> |d2=1.4 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
    |a3=V<sub>dd</sub> |d3=1.4 V
+  |a4=SRAM (HD)      |d4=2.45 µm²
 }}
 {{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
+  |xtor img=intel 90nm gate.png
    |archs=Pentium M
    |a1=L<sub>g</sub>  |d1=50 nm
    |a2=T<sub>ox</sub> |d2=1.2 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
    |a3=V<sub>dd</sub> |d3=1.2 V
+  |a4=SRAM (HD)      |d4=1.00 µm²
 }}
 {{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
@@ Line 64: / Line 86: @@
    |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
    |a3=V<sub>dd</sub> |d3=? V
+  |a4=SRAM (HD)      |d4=0.570 µm²
 }}
 {{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
@@ Line 70: / Line 93: @@
    |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
    |a3=V<sub>dd</sub> |d3=? V
+  |a4=SRAM (HD)      |d4=0.346 µm²
 }}
 {{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
    |archs=Westmere, Sandy Bridge
-   |a1=L<sub>g</sub>  |d1=30 nm
+   |a1=T<sub>ox</sub> |d1=           |a12=Gate Dielectric |d12=High-κ
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
+   |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.092 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+   |a3=L<sub>g</sub>  |d3=30 nm
+  |a4=CPP            |d4=112.5 nm   |a42=MMP             |d42=112.5 nm
 }}
 {{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
    |archs=Ivy Bridge, Haswell
-   |a1=L<sub>g</sub>  |d1=26 nm
+   |a1=T<sub>ox</sub> |d1=           |a12=Gate Dielectric |d12=High-κ
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
+   |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.092 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+   |a3=L<sub>g</sub>  |d3=26 nm
+  |a4=CPP            |d4=90 nm      |a42=MMP             |d42=80 nm
 }}
 {{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
    |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake
-   |a1=L<sub>g</sub>  |d1=20 nm
+   |a1=T<sub>ox</sub> |d1=           |a12=Gate Dielectric |d12=High-κ
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
+   |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.0499 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+   |a3=L<sub>g</sub>  |d3=20 nm
+  |a4=CPP            |d4=70 nm      |a42=MMP             |d42=52 nm
 }}
 {{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
    |archs=Cannonlake, Icelake, Tigerlake
-   |a1=L<sub>g</sub>  |d1=18? nm
+   |a1=T<sub>ox</sub> |d1=           |a12=Gate Dielectric |d12=High-κ
-   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
+   |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.0312 µm²
-   |a3=V<sub>dd</sub> |d3=? V
+   |a3=L<sub>g</sub>  |d3=18 nm ?
+  |a4=CPP            |d4=54 nm      |a42=MMP             |d42=36 nm
 }}
 {{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm
@@ Line 100: / Line 128: @@
 }}
 </table>
+</div>

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Revision as of 04:40, 11 May 2017

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