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Difference between revisions of "intel/microarchitectures/core (client)"
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(→‎Overview)
(→‎Overview)
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=== Intel Core Lines ===
 
=== Intel Core Lines ===
  
−
{| class="wikitable mw-datatable" style="margin:0.5em auto; text-align:center; min-width:72em;"
+
{| class="wikitable mw-datatable" style="margin:0.2em auto; text-align:center; min-width:75em;"
 
|+Intel Core (+ Pentium 4) Roadmap
 
|+Intel Core (+ Pentium 4) Roadmap
 
|-
 
|-
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| Prestonia<br>Gallatin
 
| Prestonia<br>Gallatin
 
| Gallatin
 
| Gallatin
−
|  
+
| &mdash;
 
|-
 
|-
 
| [[90 nm]]
 
| [[90 nm]]
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| rowspan="2" | 2018-08-28
 
| rowspan="2" | 2018-08-28
 
| Whiskey Lake-U
 
| Whiskey Lake-U
−
| colspan="4" rowspan="2" | &mdash;
+
| colspan="2" rowspan="2" | &mdash;
 +
| colspan="2" rowspan="2" | &mdash;
 
|-
 
|-
 
| [[Amber Lake]]
 
| [[Amber Lake]]
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| &mdash;
 
| &mdash;
 
| 2019-09
 
| 2019-09
−
| Comet Lake-H<br>Comet Lake-U<br>Comet Lake-Y
+
| Comet Lake-H<br>Comet Lake-Y<br>{{intel|Comet Lake U|l=core}}
−
| Comet Lake-S
+
| {{intel|Comet Lake S|l=core}}
 
| Comet Lake-W
 
| Comet Lake-W
 
| colspan="2" | &mdash;
 
| colspan="2" | &mdash;
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| 2018-05
 
| 2018-05
 
| Cannon Lake-U
 
| Cannon Lake-U
−
| colspan=4 | &mdash;
+
| colspan=2 | &mdash;
 +
| colspan=2 | &mdash;
 
|-
 
|-
 
| rowspan=2 | [[Sunny Cove]]
 
| rowspan=2 | [[Sunny Cove]]
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| 2020-06-10
 
| 2020-06-10
 
| {{intel|Lakefield|l=arch}}
 
| {{intel|Lakefield|l=arch}}
−
| colspan=4 rowspan=2 | &mdash;
+
|
 +
|
 +
|
 +
| &mdash;
 
|-
 
|-
 
| {{intel|Willow Cove|l=arch}}
 
| {{intel|Willow Cove|l=arch}}
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| 2020-09
 
| 2020-09
 
| Tiger Lake-H<br>Tiger Lake-H35<br>Tiger Lake-UP3<br>Tiger Lake-UP4
 
| Tiger Lake-H<br>Tiger Lake-H35<br>Tiger Lake-UP3<br>Tiger Lake-UP4
 +
|
 +
|
 +
|
 +
| &mdash;
 
|-
 
|-
 
| rowspan="4" | [[Intel]] [[7 nm]]
 
| rowspan="4" | [[Intel]] [[7 nm]]
−
| rowspan="2" | [[Golden Cove]]
+
| rowspan="2" | {{intel|Golden Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
−
| [[Alder Lake]]<br><small>(hybrid)</small>
+
| {{intel|Alder Lake|l=arch}}<br><small>(hybrid)</small>
 
| 12
 
| 12
 
| 2021-11-04 <!-- ? "Sunny Cove" -->
 
| 2021-11-04 <!-- ? "Sunny Cove" -->
−
| Alder Lake-H<br>Alder Lake-HX<br>Alder Lake-P<br>Alder Lake-U
+
| Alder Lake-H<br>Alder Lake-HX<br>Alder Lake-U<br>{{intel|Alder Lake M|l=core}}
−
| Alder Lake-S
+
| {{intel|Alder Lake S|l=core}}
−
| colspan=3 | &mdash;
+
| {{intel|Alder Lake P|l=core}}
 +
| colspan=2 | &mdash;
 
|-
 
|-
 
| [[Sapphire Rapids]]
 
| [[Sapphire Rapids]]
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| Sapphire <br>Rapids-SP
 
| Sapphire <br>Rapids-SP
 
|-
 
|-
−
| rowspan="2" | {{intel|Raptor Cove|l=arch}}
+
| rowspan="2" | {{intel|Raptor Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 
| {{intel|Raptor Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Raptor Lake|l=arch}}<br><small>(hybrid)</small>
 
| 13 / 14 /<br>Series<br> 1 / 2
 
| 13 / 14 /<br>Series<br> 1 / 2
 
| &mdash;
 
| &mdash;
 
| 2022-10-20
 
| 2022-10-20
−
| Raptor Lake-H<br>Raptor Lake-HX<br>Raptor Lake-P<br>Raptor Lake-PX<br>Raptor Lake-U
+
| Raptor Lake-HX<br>Raptor Lake-PX<br>Raptor Lake U
−
| Raptor Lake-S
+
| Raptor Lake S
−
| &mdash;
+
| Raptor Lake H<br>Raptor Lake P
 
| Raptor Lake<br>(Xeon E)
 
| Raptor Lake<br>(Xeon E)
 
| rowspan=2 | &mdash;
 
| rowspan=2 | &mdash;
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|-
 
|-
 
| [[Intel]] [[4 nm]]
 
| [[Intel]] [[4 nm]]
−
| rowspan="2" | {{intel|Redwood Cove|l=arch}}
+
| rowspan="2" | {{intel|Redwood Cove|l=arch}} (P)<br>{{intel|Crestmont|l=arch}} (E)
 
| {{intel|Meteor Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Meteor Lake|l=arch}}<br><small>(hybrid)</small>
 
| Ultra <br>Series 1
 
| Ultra <br>Series 1
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| 2023-12-14
 
| 2023-12-14
 
| Meteor Lake-H<br>Meteor Lake-U
 
| Meteor Lake-H<br>Meteor Lake-U
−
| colspan="4" | &mdash;
+
| colspan="2" | &mdash;
 +
| colspan="2" | &mdash;
 
|-
 
|-
 
| [[Intel]] [[3 nm]]
 
| [[Intel]] [[3 nm]]
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|-
 
|-
 
| rowspan="2" | TSMC N3B
 
| rowspan="2" | TSMC N3B
−
| rowspan="2" | {{intel|Lion Cove|l=arch}}
+
| rowspan="2" | {{intel|Lion Cove|l=arch}} (P)<br>{{intel|Skymont|l=arch}} (E)
 
| {{intel|Lunar Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Lunar Lake|l=arch}}<br><small>(hybrid)</small>
 
| Ultra<br>200V <!-- Core Ultra 200V -->
 
| Ultra<br>200V <!-- Core Ultra 200V -->
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| 2024-09
 
| 2024-09
 
| Lunar Lake-V
 
| Lunar Lake-V
−
| colspan=4 | &mdash;
+
| colspan=2 | &mdash;
 +
| colspan=2 | &mdash;
 
|-
 
|-
 
| {{intel|Arrow Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Arrow Lake|l=arch}}<br><small>(hybrid)</small>
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| Arrow Lake-H<br>Arrow Lake-HX<br>Arrow Lake-U
 
| Arrow Lake-H<br>Arrow Lake-HX<br>Arrow Lake-U
 
| Arrow Lake-S
 
| Arrow Lake-S
−
| colspan=3 rowspan=2 | &mdash;
+
|  
 +
| &mdash;
 +
| &mdash;
 
|-
 
|-
 
| rowspan="2" | [[Intel]] 18A
 
| rowspan="2" | [[Intel]] 18A
−
| {{intel|Cougar Cove|l=arch}} <!-- Cougar Cove (P-cores), Darkmont (E-cores) -->
+
| {{intel|Cougar Cove|l=arch}} (P)<br>{{intel|Darkmont|l=arch}} (E) <!-- Cougar Cove (P-cores), Darkmont (E-cores) -->
 
| {{intel|Panther Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Panther Lake|l=arch}}<br><small>(hybrid)</small>
 
| Ultra <br>300 <!-- Core Ultra 300 -->
 
| Ultra <br>300 <!-- Core Ultra 300 -->
 
| 2025
 
| 2025
−
| Panther Lake-H<br>Panther Lake-U<br>Panther Lake-HL<br>Panther Lake-UL
+
| Panther Lake-H<br>Panther Lake-HL<br>Panther Lake-U<br>Panther Lake-UL
 
| ?
 
| ?
 +
|
 +
| &mdash;
 +
| &mdash;
 
|-
 
|-
 
| {{intel|Panther Cove X|l=arch}} <!-- Panther Cove X, Mountain Stream -->
 
| {{intel|Panther Cove X|l=arch}} <!-- Panther Cove X, Mountain Stream -->
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|  
 
|  
 
|  
 
|  
−
|  
+
| &mdash;
−
| -
+
| &mdash;
 
|-
 
|-
 
| rowspan="2" | TBA<br>(TSMC <br>2&nbsp;nm or<br>Intel 18A)
 
| rowspan="2" | TBA<br>(TSMC <br>2&nbsp;nm or<br>Intel 18A)
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| TBA
 
| TBA
 
| TBA
 
| TBA
−
|  
+
| &mdash;
−
| -
+
| &mdash;
 
|-
 
|-
 
|  
 
|  
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| TBA
 
| TBA
 
| TBA
 
| TBA
−
|  
+
| &mdash;
−
| -
+
| &mdash;
 
|-
 
|-
 
|}
 
|}

Revision as of 09:11, 25 February 2025

Edit Values
Core µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionApril, 2006
Phase-outMay, 2009
Process65 nm
Instructions
ISAx86-64
Succession

Core was the microarchitecture for Intel's 65 nm process for desktops and servers as a successor to NetBurst. Core was replaced by the Penryn microarchitecture in late 2008.

Architecture

New text document.svg This section is empty; you can help add the missing info by editing this page.

Key changes from NetBurst

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview

  • When Core was introduced in 2006, Intel described it as a merger of both P6 and NetBurst.
When scrutinizing the details, it's fairly clear that little was actually borrowed from NetBurst.
In fact, it wasn't until Intel's entirely new microarchitecture Sandy Bridge that a true merger presented itself.
New text document.svg This section requires expansion; you can help adding the missing info.


Intel Core Lines

Intel Core (+ Pentium 4) Roadmap
Fab
process 		Micro-
architecture 		Code
names 		Core
Gen 		Scalable
(Xeon)
Gen 		Release
date 		Processors
Mobile Desktop Enthusiast/
Workstation 		1P/2P
Server 		4P/8P
Server
180 nm P6,
NetBurst 		Willamette — 2000-11-20 — Willamette — Foster Foster MP
130 nm Northwood
/ Mobile
Pentium 4
Banias (P-M) 		2002-01-07 Northwood
Mobile
Banias 		Northwood
(-XE) 		Prestonia
Gallatin 		Gallatin —
90 nm Prescott
Dothan 		2004-02-01 Dothan Prescott
Smithfield 		Prescott 2M-XE
Smithfield-XE 		Nocona
Irwindale
Paxville 		Potomac
Cranford
Paxville
65 nm Cedar Mill
Yonah
Presler 		1
(Yonah
only) 		— 2006-01-05 Yonah Cedar Mill
Presler (P-D) 		Presler-XE Dempsey
Sossaman 		Xeon "Tulsa"
(65 nm)
Intel Core Merom 2 2006-07-27 Merom Conroe Kentsfield Woodcrest
Clovertown 		Tigerton
45 nm Penryn 2007-11-11 Penryn Wolfdale Yorkfield Harpertown Dunnington
Nehalem Nehalem 1
(Core i) 		2008-11-17 Clarksfield Lynnfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01-04 Arrandale Clarkdale Gulftown Westmere-EP Westmere-EX
Sandy Bridge Sandy Bridge 2 2011-01-09 Sandy Bridge-M Sandy Bridge Sandy Bridge-E Sandy Bridge-EP —
22 nm Ivy Bridge 3 2012-04-29 Ivy Bridge-M Ivy Bridge Ivy Bridge-E Ivy Bridge-EP Ivy Bridge-EX
Haswell Haswell 4 2013-06-0 Haswell-H
Haswell-MB
Haswell-ULP/ULX 		Haswell-DT Haswell-E Haswell-EP Haswell-EX
Devil's Canyon 2014-06 — Haswell-DT —
14 nm Broadwell 5 2014-09-05 Broadwell-H
Broadwell-U
Broadwell-Y 		Broadwell-DT Broadwell-E Broadwell-EP Broadwell-EX
Skylake Skylake 6 1 2015-08-05 Skylake-H
Skylake-U
Skylake-Y 		Skylake-S Skylake-W
Skylake-X 		Skylake-SP
(formerly Skylake-EP/EX)
(Xeon Gold, Platinum)
Kaby Lake 7 / 8 — 2016-10 Kaby Lake-G
Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y 		Kaby Lake-S Kaby Lake-X —
Coffee Lake 8 / 9 2017-10 Coffee Lake-B
Coffee Lake-H
Coffee Lake-U 		Coffee Lake-S Coffee Lake-W Coffee Lake
(Xeon E) 		—
Whiskey Lake 8 2018-08-28 Whiskey Lake-U — —
Amber Lake 8 / 10 Amber Lake-Y
Cascade Lake — 2 2019-04-02 — Cascade Lake-W
Cascade Lake-X 		Cascade
Lake-AP/SP
Comet Lake 10 — 2019-09 Comet Lake-H
Comet Lake-Y
Comet Lake U 		Comet Lake S Comet Lake-W —
Cooper Lake — 3 2020-06 — Cooper Lake-SP
Cypress Cove Rocket Lake 11 — 2021-03 — Rocket Lake-S Rocket Lake-W Rocket Lake
(Xeon E) 		—
10 nm Palm Cove Cannon Lake 8 2018-05 Cannon Lake-U — —
Sunny Cove Ice Lake 10 3 2019-09
(mobile)
2021-04
(server) 		Ice Lake-U
Ice Lake-Y 		— Ice Lake-W Ice Lake-SP —
Lakefield
(hybrid) 		— — 2020-06-10 Lakefield —
Willow Cove Tiger Lake 11 2020-09 Tiger Lake-H
Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4 		—
Intel 7 nm Golden Cove (P)
Gracemont (E) 		Alder Lake
(hybrid) 		12 2021-11-04 Alder Lake-H
Alder Lake-HX
Alder Lake-U
Alder Lake M 		Alder Lake S Alder Lake P —
Sapphire Rapids — 4 2023-01-10 — Sapphire
Rapids-WS 		Sapphire
Rapids-SP/HBM
(Xeon Max) 		Sapphire
Rapids-SP
Raptor Cove (P)
Gracemont (E) 		Raptor Lake
(hybrid) 		13 / 14 /
Series
1 / 2 		— 2022-10-20 Raptor Lake-HX
Raptor Lake-PX
Raptor Lake U 		Raptor Lake S Raptor Lake H
Raptor Lake P 		Raptor Lake
(Xeon E) 		—
Emerald Rapids — 5 2023-12-14 — Emerald
Rapids-SP
Intel 4 nm Redwood Cove (P)
Crestmont (E) 		Meteor Lake
(hybrid) 		Ultra
Series 1 		— 2023-12-14 Meteor Lake-H
Meteor Lake-U 		— —
Intel 3 nm Granite Rapids — Xeon 6 2024-09-24 — Granite Rapids-AP
Granite Rapids-SP 		—
TSMC N3B Lion Cove (P)
Skymont (E) 		Lunar Lake
(hybrid) 		Ultra
200V 		— 2024-09 Lunar Lake-V — —
Arrow Lake
(hybrid) 		Ultra
Series 2 		2024-10-24
(desktop)
2025-01-06
(mobile) 		Arrow Lake-H
Arrow Lake-HX
Arrow Lake-U 		Arrow Lake-S — —
Intel 18A Cougar Cove (P)
Darkmont (E) 		Panther Lake
(hybrid) 		Ultra
300 		2025 Panther Lake-H
Panther Lake-HL
Panther Lake-U
Panther Lake-UL 		 ? — —
Panther Cove X Diamond Rapids — 2025 — — —
TBA
(TSMC
2 nm or
Intel 18A) 		Coyote Cove Nova Lake
(hybrid) 		— 2026 — TBA TBA — —
Razer Lake
(hybrid) 		— 2027 — TBA TBA — —

Die Shot

Dual-core Core

  • Woodcrest
  • 143 mm²
  • 291,000,000 transistors
  • 65 nm process
  • 2 cores
intel woodcrest die shot.jpg

Documents


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Facts about "Core - Microarchitectures - Intel"
RDF feed
codenameCore +
designerIntel +
first launchedApril 2006 +
full page nameintel/microarchitectures/core (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCore +
phase-outMay 2009 +
process65 nm (0.065 μm, 6.5e-5 mm) +