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Difference between revisions of "intel/microarchitectures/willow cove"
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*50% increase in L3 cache per core (3Mb up from 2Mb) | *50% increase in L3 cache per core (3Mb up from 2Mb) | ||
*Increased IPC compared to sunny cove | *Increased IPC compared to sunny cove | ||
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Revision as of 21:14, 11 June 2020
| Edit Values | |
| Willow Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2020 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Willow Cove is the successor to Sunny Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products, including Tiger Lake.
Contents
History
Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.
Process Technology
Willow Cove is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Sunny Cove
- New cache subsystem
- Security features
- 125% increase in L2 cache per core (1.25Mb up from 0.5 Mb)
- 50% increase in L3 cache per core (3Mb up from 2Mb)
- Increased IPC compared to sunny cove
This list is incomplete; you can help by expanding it.
New instructions
Willow Cove introduced a number of new instructions:
- Control-flow Enforcement Technology (CET) enhancements
-
MOVDIR- Direct stores - Additional AVX-512 extensions:
-
AVX512_VP2INTERSECT- AVX-512 Vector Intersection Instructions
-
Only on server parts (Sapphire Rapids):
-
ENQCMD- Enqueue Stores
Bibliography
- Intel Architecture Day 2018, December 11, 2018
Facts about "Willow Cove - Microarchitectures - Intel"
| codename | Willow Cove + |
| designer | Intel + |
| first launched | 2020 + |
| full page name | intel/microarchitectures/willow cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Willow Cove + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |