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Difference between revisions of "samsung/exynos/990"
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(exynos 990)
 
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'''Exynos 990''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in [[2020]]. The processor is fabricated on Samsung's [[7 nm process|7nm]] EUV FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose 5|l=arch}} [[big cores]], 2 {{armh|Cortex-A75|l=arch}} [[middle cores]], and 4 Cortex-A55 [[little cores]]. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR5-5500 memory and incorporates a {{armh|Mali-G77}} MP11 GPU. The 990 is designed to go along with Exynos Modem 5123 5G modem.
 
'''Exynos 990''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in [[2020]]. The processor is fabricated on Samsung's [[7 nm process|7nm]] EUV FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose 5|l=arch}} [[big cores]], 2 {{armh|Cortex-A75|l=arch}} [[middle cores]], and 4 Cortex-A55 [[little cores]]. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR5-5500 memory and incorporates a {{armh|Mali-G77}} MP11 GPU. The 990 is designed to go along with Exynos Modem 5123 5G modem.
 +
 +
== Cache ==
 +
{{main|samsung/microarchitectures/m5#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Mongoose 5  § Cache||l2=Cortex-A76 § Cache}}
 +
For the {{samsung|Mongoose 5|l=arch}} core cluster:
 +
 +
{{future information}}
 +
{{cache size
 +
|l1 cache=192 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=2x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=1 MiB
 +
|l2 break=2x512 KiB
 +
|l2 desc=16-way set associative
 +
|l3 cache=2 MiB
 +
|l3 break=2x1 MiB
 +
}}
 +
 +
For the {{armh|Cortex-A75|l=arch}} cluster:
 +
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=2x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=2x64 KiB
 +
|l1d desc=16-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
 +
For the {{armh|Cortex-A55|l=arch}} cluster:
 +
 +
{{cache size
 +
|l1 cache=
 +
|l1i cache=
 +
|l1i break=
 +
|l1i desc=
 +
|l1d cache=
 +
|l1d break=
 +
|l1d desc=
 +
|l2 cache=
 +
|l2 break=
 +
|l2 desc=
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4X-3600
 +
|ecc=No
 +
|max mem=12 GiB
 +
|controllers=4
 +
|channels=4
 +
|width=16 bit
 +
|max bandwidth=26.82 GiB/s
 +
|frequency=1800 MHz
 +
|bandwidth schan=6.71 GiB/s
 +
|bandwidth dchan=13.41 GiB/s
 +
|bandwidth qchan=26.82 GiB/s
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-G77
 +
| device id          =
 +
| designer            = ARM Holdings
 +
| execution units    = 11
 +
| max displays        = 2
 +
| max memory          =
 +
| frequency          = ? MHz
 +
| max frequency      =
 +
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          = Yes
 +
| output edp          =
 +
| output dp          =
 +
| output hdmi        =
 +
| output vga          =
 +
| output dvi          =
 +
 +
| directx ver        = 12
 +
| opengl ver        =
 +
| opengl es ver      = 3.2
 +
| openvg ver        = 1.1
 +
| opencl ver        = 2
 +
| vulkan ver        = 1.0
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
 +
 +
{| class=wikitable
 +
|-
 +
! Codec !! Encode !! Decode
 +
|-
 +
| [[HEVC]] (H.265) || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
| [[MPEG-4 AVC]] (H.264) || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
| [[VP9]] || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
|}
 +
 +
All at 4K UHD 150fps.
 +
 +
== ISP ==
 +
* 108MP Rear
 +
* 24.8MP Front
 +
* 24.8MP+24.8MP Dual
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=No
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=No
 +
|crc32=Yes
 +
|crypto=Yes
 +
|fp=Yes
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
 +
|rdm=No
 +
}}
 +
 +
== Utilizing devices ==
 +
* [[used by::Samsung Galaxy S11]]
 +
{{expand list}}

Revision as of 00:21, 4 December 2019

Edit Values
Exynos 990
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number990
MarketMobile
IntroductionOctober 23, 2019 (announced)
2020 (launched)
General Specs
FamilyExynos
SeriesExynos 9
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureMongoose 5, Cortex-A76, Cortex-A55
Core NameMongoose 5, Cortex-A76, Cortex-A55
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory12 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Succession

Exynos 990 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in 2020. The processor is fabricated on Samsung's 7nm EUV FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 5 big cores, 2 Cortex-A75 middle cores, and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR5-5500 memory and incorporates a Mali-G77 MP11 GPU. The 990 is designed to go along with Exynos Modem 5123 5G modem.

Cache

Main articles: Mongoose 5 § Cache and Cortex-A76 § Cache

For the Mongoose 5 core cluster:

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB16-way set associative 
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB  

For the Cortex-A75 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
2x64 KiB16-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associative 


For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3600
Supports ECCNo
Max Mem12 GiB
Frequency1800 MHz
Controllers4
Channels4
Width16 bit
Max Bandwidth26.82 GiB/s
27,463.68 MiB/s
28.798 GB/s
28,797.756 MB/s
0.0262 TiB/s
0.0288 TB/s
Bandwidth
Single 6.71 GiB/s
Double 13.41 GiB/s
Quad 26.82 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G77
DesignerARM Holdings
Execution Units11Max Displays2
Frequency? MHz
"? MHz" is not a number.
OutputDSI
Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Codec Encode Decode
HEVC (H.265) ✔ ✔
MPEG-4 AVC (H.264) ✔ ✔
VP9 ✔ ✔

All at 4K UHD 150fps.

ISP

  • 108MP Rear
  • 24.8MP Front
  • 24.8MP+24.8MP Dual

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices

  • Samsung Galaxy S11

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/990&oldid=94736"
Facts about "Exynos 990 - Samsung"
RDF feed
base frequency3,016 MHz (3.016 GHz, 3,016,000 kHz) +, 2,600 MHz (2.6 GHz, 2,600,000 kHz) + and 2,106 MHz (2.106 GHz, 2,106,000 kHz) +
core count8 +
core nameMongoose 5 +, Cortex-A76 + and Cortex-A55 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedOctober 23, 2019 +
first launched2020 +
full page namesamsung/exynos/990 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuMali-G77 +
integrated gpu base frequency832 MHz (0.832 GHz, 832,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units11 +
isaARMv8.2 +
isa familyARM +
l1$ size192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 16-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative + and 16-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate2020 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth40.978 GiB/s (41,961.67 MiB/s, 44 GB/s, 44,000 MB/s, 0.04 TiB/s, 0.044 TB/s) +
max memory channels4 +
microarchitectureMongoose 5 +, Cortex-A76 + and Cortex-A55 +
min junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
model number990 +
nameExynos 9830 +
process7 nm (0.007 μm, 7.0e-6 mm) +
seriesExynos 9 +
smp max ways1 +
supported memory typeLPDDR5-5500 +
tdp8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp down8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp up15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
technologyCMOS +
thread count8 +
used bySamsung Galaxy S20 Series + and Samsung Galaxy Note 20 Series +
word size64 bit (8 octets, 16 nibbles) +