From WikiChip
Difference between revisions of "amd/epyc/7232p"
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|bandwidth hchan=143.1 GiB/s | |bandwidth hchan=143.1 GiB/s | ||
|bandwidth ochan=190.7 GiB/s | |bandwidth ochan=190.7 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 4.0 | ||
+ | | pcie lanes = 128 | ||
+ | | pcie config = 8x16 | ||
+ | | pcie config 2 = 32x4 | ||
+ | | sata revision = | ||
+ | | sata ports = | ||
+ | | usb revision = | ||
+ | | usb revision 2 = | ||
+ | | usb ports = | ||
+ | | usb rate = | ||
+ | | uart = | ||
+ | | uart ports = | ||
+ | | gp io = | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=Yes | ||
+ | |amdtsme=Yes | ||
+ | |amdsev=Yes | ||
+ | |rvi=No | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=No | ||
}} | }} |
Revision as of 17:44, 6 August 2019
Edit Values | |
EPYC 7252P | |
General Info | |
Designer | AMD |
Manufacturer | TSMC, GlobalFoundries |
Model Number | 7252P |
Part Number | 100-000000081 |
Market | Server |
Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7002 |
Locked | Yes |
Frequency | 2,800 MHz |
Turbo Frequency | 3,200 MHz |
Clock multiplier | 28 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 2 |
Core Name | Rome |
Core Family | 23 |
Process | 7 nm, 14 nm |
Technology | CMOS |
MCP | Yes (3 dies) |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 4 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 120 W |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7252P is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7252P has a TDP of 120 W with a base frequency of 2.8 GHz and a boost frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
Contents
Cache
- Main article: Zen 2 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
Facts about "EPYC 7232P - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7232P - AMD#io + |
base frequency | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
clock multiplier | 28 + |
core count | 8 + |
core family | 23 + |
core name | Rome + |
designer | AMD + |
die count | 3 + |
family | EPYC + |
first announced | August 7, 2019 + |
first launched | August 7, 2019 + |
full page name | amd/epyc/7232p + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | August 7, 2019 + |
manufacturer | TSMC + and GlobalFoundries + |
market segment | Server + |
max cpu count | 1 + |
max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
microarchitecture | Zen 2 + |
model number | 7252P + |
name | EPYC 7252P + |
package | SP3 + and FCLGA-4094 + |
part number | 100-000000081 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 7002 + |
smp max ways | 1 + |
socket | SP3 + and LGA-4094 + |
supported memory type | DDR4-3200 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |