From WikiChip
Difference between revisions of "amd/epyc/7542"
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|l3 cache=128 MiB | |l3 cache=128 MiB | ||
|l3 break=8x16 MiB | |l3 break=8x16 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-3200 | ||
+ | |ecc=Yes | ||
+ | |max mem=4 TiB | ||
+ | |controllers=8 | ||
+ | |channels=8 | ||
+ | |max bandwidth=190.7 GiB/s | ||
+ | |bandwidth schan=23.84 GiB/s | ||
+ | |bandwidth dchan=47.68 GiB/s | ||
+ | |bandwidth qchan=95.37 GiB/s | ||
+ | |bandwidth hchan=143.1 GiB/s | ||
+ | |bandwidth ochan=190.7 GiB/s | ||
}} | }} |
Revision as of 15:54, 6 August 2019
Edit Values | |
EPYC 7542 | |
General Info | |
Designer | AMD |
Manufacturer | TSMC, GlobalFoundries |
Model Number | 7542 |
Part Number | 100-000000075 |
Market | Server |
Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7002 |
Locked | Yes |
Frequency | 2,900 MHz |
Turbo Frequency | 3,400 MHz |
Clock multiplier | 29 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 2 |
Core Name | Rome |
Core Family | 23 |
Process | 7 nm, 14 nm |
Technology | CMOS |
MCP | Yes (5 dies) |
Word Size | 64 bit |
Cores | 32 |
Threads | 64 |
Max Memory | 4 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 225 W |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7542 is a 64-bit dotriaconta-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7542 has a TDP of 225 W with a base frequency of 2.9 GHz and a boost frequency of up to 3.4 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.
Cache
- Main article: Zen 2 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "EPYC 7542 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7542 - AMD#pcie + |
base frequency | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
clock multiplier | 29 + |
core count | 32 + |
core family | 23 + |
core model | 49 + |
core name | Rome + |
core stepping | B0 + |
designer | AMD + |
die count | 5 + |
family | EPYC + |
first announced | August 7, 2019 + |
first launched | August 7, 2019 + |
full page name | amd/epyc/7542 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd precision boost 2 | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ size | 128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) + |
ldate | August 7, 2019 + |
manufacturer | TSMC + and GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
max memory channels | 8 + |
microarchitecture | Zen 2 + |
model number | 7542 + |
name | EPYC 7542 + |
package | FCLGA-4094 + and SP3 + |
part number | 100-000000075 + and 100-100000075WOF + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,400.00 (€ 3,060.00, £ 2,754.00, ¥ 351,322.00) + |
series | 7002 + |
smp max ways | 2 + |
socket | LGA-4094 + and SP3 + |
supported memory type | DDR4-3200 + |
tdp | 225 W (225,000 mW, 0.302 hp, 0.225 kW) + |
technology | CMOS + |
thread count | 64 + |
turbo frequency | 3,400 MHz (3.4 GHz, 3,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |