Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/microarchitectures/taishan v110"
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Revision as of 12:08, 2 May 2019
| Edit Values | |
| TaiShan µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | HiSilicon |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 7 nm |
| Core Configs | 32, 48, 64 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 4-way |
| Instructions | |
| ISA | ARMv8.2-A |
| Extensions | NEON |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| L2 Cache | 512 KiB/core |
| L3 Cache | 1 MiB/core |
| Cores | |
| Core Names | TaiShan |
TaiShan is a high-performance ARM server microarchitecture designed by HiSilicon for Huawei's own TaiShan servers.
Contents
Brands
TaiShan-based CPUs are branded as the Kunpeng 920 series.
Release Dates
Kunpeng 920 CPUs were officially launched in early 2019.
Architecture
This list is incomplete; you can help by expanding it.
Block Diagram
Entire Chip
Memory Hierarchy
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This section is empty; you can help add the missing info by editing this page. |
Overview
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This section is empty; you can help add the missing info by editing this page. |
Core
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This section is empty; you can help add the missing info by editing this page. |
Scalability
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This section is empty; you can help add the missing info by editing this page. |
Die
- TSMC 7 nm HPC
- 20,000,000,000 transistors
All TaiShan Chips
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This section is empty; you can help add the missing info by editing this page. |
Bibliography
- Huawei. Personal Communication. 2019
- Huawei Connect 2018. October 2018
- HiSilicon Event. January 7, 2019
Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
| codename | TaiShan + |
| core count | 32 +, 48 + and 64 + |
| designer | HiSilicon + |
| first launched | 2019 + |
| full page name | hisilicon/microarchitectures/taishan v110 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | TaiShan + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |