Revision as of 23:57, 9 April 2018

Broadwell (BDW) is Intel's microarchitecture based on the 14 nm process for mobile, desktops, and servers. Introduced in early 2015, Broadwell is a process shrink of Haswell which introduced several enhancements. Broadwell is named after Broadwell, Illinois.

For desktop and mobile, Broadwell is branded as 5th Generation Intel Core processors. For server class processors, Intel branded it as Xeon E3 v4, Xeon E5 v4, and Xeon E7 v4.

Codenames

Process Technology

Broadwell is designed to be manufactured using 14 nm Tri-gate FinFET transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high performance and high density.

Scaling:

	Haswell	Broadwell	Δ
	22 nm	14 nm
Fin Pitch	60 nm	42	0.70x
Fin Width​	8 nm	8 nm	1x
Fin Height​	34 nm	42 nm	1.24x
Gate Pitch	90 nm	70 nm	0.78x
Interconnect Pitch	80 nm	52 nm	0.65x
Cell Height	840 nm	399 nm	0.48x

Architecture

Broadwell is for the most part identical to Haswell with several enhancements, including new instruction set extensions.

Key changes from Haswell

• ~5% IPC improvement
• FP multiplication instructions has reduced latency (3 cycles, down from 5)
  • Affects AVX, SSE, and FP instructions
• CLMUL instructions are now a single μop, improving latency and throughput
• The second-level TLB (STLB)
  • Table was enlarged (1,536 entries, up from 1024)
  • 1GB page mode (16 entries, 4-ways set associative)
• Execution Engine
  • Larger scheduler (64 entries, up from 60)
  • Larger instruction queue (25 entries/thread, up from 20)
  • Faster store-to-load forwarding
  • Address prediction for branches and returns was improved
  • Improved cryptography acceleration instructions

Core features maintained a 2:1 ratio of performance:power.

Graphics

• 50% higher sampler throughput
• Improvements for increased geometry, Z, Pixel Fill
• Direct X 11.2, OpenGL 4.3
• OpenCL 1.2 and 2.0 (with Shared Virtual Memory)
• Up to 24 EUs (20% addition, up from 20 in Haswell), 48 EUs on Iris Pro Graphics

New instructions

Broadwell introduced a number of new instructions:

• RDSEED - Generates 16, 32 or 64 bit random numbers seeds (NIST SP 800-90B & NIST SP 800-90C)
• ADCX - Arbitrary precision integer operations
• PREFETCHW - Prefetch data into caches, hinting a write is expected in the future
• SMAP - Supervisor Mode Access Prevention

Block Diagram

Memory Hierarchy

Broadwell Xeon D wafer

• Cache
  • L1 Cache:
    • 32 KiB 8-way set associative instruction, 64 B line size
    • 32 KiB 8-way set associative data, 64 B line size
    • Write-back policy
    • Per core
  • L2 Cache:
    • 256 KiB 8-way set associative, 64 B line size
    • Write-back policy
    • Per core
  • L3 Cache:
    • 1.5 - 3 MiB per core, 64 B line size
    • 16-20 -way set associative
    • Write-back policy
  • L4 Cache:
    • 128 MiB
    • eDRAM
    • shared with GPU (Crystal Well)
    • Iris Pro models only

Broadwell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 4-way set associative
      • dynamic partition; divided between the two threads
    • 2 MiB / 4MiB page translations:
      • 8 entries; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition; divided between the two threads
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
    • 1 GiB page translations:
      • 4 entries; 4-way set associative
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 6-way set associative
      • shared
    • 1 GiB page translations:
      • 16 entries; 4-way set associative

Pipeline

Main article: Haswell's Pipeline

Broadwell's pipeline is identical to Haswell.

High Core count (EP)

• Key Changes from Haswell:
  • Up to 22 cores (up from 18)
  • Up to 44 threads (up from 36)
  • Up to 55 MiB LLC (up from 45 MiB)
  • Up to 2400 DDR (from 2133)

This section requires expansion; you can help adding the missing info.

Snoop Modes

Broadwell EP has four snoop modes: Home Snoop (HS), Early Snoop (ES), Cluster-on-Die (COD) and Home Snoop with Directory and Opportunistic Snoop Broadcast (HS with DIR + OSB).

¹ - Performance depends on the directory state. Expect low latency with a clean directory and high latency with a dirty directory.

Die Stats

Layout
Low Core Count (LCC)	Medium Core Count (MCC)	High Core Count (HCC)
Up to 10 Cores	12-14 Cores	16+ Cores
246.24 mm²	306.18 mm²	456.12 mm²
~3,200,000,000 Transistors	~4,700,000,000 Transistors	~7,200,000,000 Transistors

Die

Dual-core

• 14 nm process
• 13 metal layers
• 1,300,000,000 transistors
• 82 mm² die size
• 2 cores

Dual-core Broadwell with Iris Pro die

• 14 nm process
• 13 metal layers
• 1,900,000,000 transistors
• 133 mm² die size
• 2 cores

Quad-core Broadwell with Iris Pro die

Die shot of the Core i7-5775C microprocessor.

• 14 nm process
• 13 metal layers
•  ? transistors
•  ? mm² die size
• 4 cores

Deca-core Broadwell

Die shot of the Core i7-6950X microprocessor.

• 14 nm process
•  ? metal layers
• 3,400,000,000 transistors
• 246 mm² die size
• 10 cores

Added instructions

RDSEED - Generates 16, 32 or 64 bit random numbers seeds (both NIST SP 800-90B and NIST SP 800-90C compliant)

ADCX - Arbitrary precision integer operations

PREFETCHW - Prefetch data into caches, hinting a write is expected in the future.

Cores

This section is empty; you can help add the missing info by editing this page.

All Broadwell Chips