Revision as of 17:13, 27 March 2018

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Exynos 9810
General Info
Designer	Samsung, ARM Holdings
Manufacturer	Samsung
Model Number	9810
Market	Mobile
Introduction	January 3, 2018 (announced) February 25, 2018 (launched)
General Specs
Family	Exynos
Series	9000
Frequency	2,900 MHz, 1,900 MHz
Microarchitecture
ISA	ARMv8.3 (ARM)
Microarchitecture	Mongoose 3, Cortex-A55
Core Name	Mongoose 3, Cortex-A55
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a DynamiQ configuration consisting of 4 Mongoose 3 cores operating at 2.9 GHz and 4 Cortex-A55 cores operating at 1.9 GHz. The chip incorporates a Mali-G72 (MP18) GPU and a 1.2 Gbps LTE modem.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache

For the Mongoose 3 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 6x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB 16-way set associative

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 2-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-3600 Supports ECC No Max Mem 6 GiB Frequency 1800 MHz Controllers 2 Channels 2 Width 32 bit Bandwidth Single 13.41 GiB/s Double 26.82 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G72 Designer ARM Holdings Execution Units 18 Max Displays 2 Frequency 600 MHz 0.6 GHz 600,000 KHz Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Utilizing devices

• Samsung Galaxy S9
• Samsung Galaxy S9+

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