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Difference between revisions of "intel/microarchitectures/ice lake (client)"
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| successor link = intel/microarchitectures/tigerlake | | successor link = intel/microarchitectures/tigerlake | ||
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| − | '''Icelake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Cannonlake}}. Icelake is expected to be fabricated using a [[10 nm process]]. Icelake is the "Architecture" microarchitecture as part of Intel's {{intel|PAO}} model. | + | '''Icelake''' ('''ICL''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Cannonlake}}. Icelake is expected to be fabricated using a [[10 nm process]]. Icelake is the "Architecture" microarchitecture as part of Intel's {{intel|PAO}} model. |
== Process Technology== | == Process Technology== | ||
{{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | {{main|intel/microarchitectures/cannonlake#Process_Technology|l1=Cannonlake § Process Technology}} | ||
Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | Tigerlake is set to use the same [[10 nm process]] that was designed for Cannonlake. | ||
Revision as of 13:18, 9 June 2017
| Edit Values | |
| Icelake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018 |
| Process | 10 nm |
| Succession | |
Icelake (ICL) is a planned microarchitecture by Intel as a successor to Cannonlake. Icelake is expected to be fabricated using a 10 nm process. Icelake is the "Architecture" microarchitecture as part of Intel's PAO model.
Process Technology
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
Facts about "Ice Lake (client) - Microarchitectures - Intel"
| codename | Ice Lake (client) + |
| core count | 2 + and 4 + |
| designer | Intel + |
| first launched | May 27, 2019 + |
| full page name | intel/microarchitectures/ice lake (client) + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Ice Lake (client) + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |