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{{title|HiSilicon CPU series}}
 +
 
==[[HiSilicon]]==
 
==[[HiSilicon]]==
 +
 +
=== Family ===
 +
{{collist
 +
| count = 4
 +
|
 +
* {{hisil|Hi16xx}}
 +
* {{hisil|Hi3xxx}}
 +
* {{hisil|K3}}
 +
* {{hisil|Kirin}}
 +
* {{hisil|Ascend}}
 +
* {{hisil|Balong}}
 +
* {{hisil|Kunpeng}}
 +
* {{hisil|taishan_v110|TaiShan|l=arch}} (uarch)
 +
}}
 +
 +
:;[[Kirin]]
 +
:{{hisil|taishan_v110|TaiShan|l=arch}} (uarch)
  
 
=== Kirin 9000E, 9000L, 9000 5G/4G series ===
 
=== Kirin 9000E, 9000L, 9000 5G/4G series ===
Line 5: Line 24:
 
:and the first [[5 nm]] SoC to be launched on the international market. <ref>{{cite book |title=Kirin 9000 |website=hisilicon.com |url=https://www.hisilicon.com/en/products/Kirin/Kirin-flagship-chips/Kirin-9000 |date=16 September 2021}}</ref>  
 
:and the first [[5 nm]] SoC to be launched on the international market. <ref>{{cite book |title=Kirin 9000 |website=hisilicon.com |url=https://www.hisilicon.com/en/products/Kirin/Kirin-flagship-chips/Kirin-9000 |date=16 September 2021}}</ref>  
  
−
This [[octa-core]] [[system on a chip]] is based on the 9th Gen of the [[HiSilicon]] [[Kirin]]  
+
This [[octa-core]] [[system on a chip]] is based on the 9th Gen of the [[HiSilicon]] [[Kirin]] series
−
:series and is equipped with 15.3 billion transistors in a 1+3+4 core configuration:  
+
:and is equipped with 15.3 billion transistors in a 1+3+4 core configuration:  
 
*4x ARM Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz),  
 
*4x ARM Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz),  
 
*4x ARM Cortex-A55 (4x 2.05 GHz) and  
 
*4x ARM Cortex-A55 (4x 2.05 GHz) and  
Line 54: Line 73:
 
! Band width <br>(GB/s)
 
! Band width <br>(GB/s)
 
|-
 
|-
−
! Kirin 9000L
+
| '''Kirin 9000L'''
 
| rowspan="3" | [[TSMC]] [[5 nm]]+ <br>[[FinFET]] ([[EUV]])
 
| rowspan="3" | [[TSMC]] [[5 nm]]+ <br>[[FinFET]] ([[EUV]])
 
| rowspan="3" |[[ARMv8|ARM<br>v8.2-A]]
 
| rowspan="3" |[[ARMv8|ARM<br>v8.2-A]]
Line 67: Line 86:
 
| rowspan="3" | Q4 2020
 
| rowspan="3" | Q4 2020
 
|-
 
|-
−
! Kirin 9000E
+
| '''Kirin 9000E'''
 
| rowspan="2" | (1+3)+4
 
| rowspan="2" | (1+3)+4
 
|-
 
|-
−
! Kirin 9000<br>(Hi36A0V101)<br>Kirin 9000 4G<br>Kirin 9000 5G
+
| '''Kirin 9000'''<br>(Hi36A0V101)<br>'''Kirin 9000 4G'''<br>'''Kirin 9000 5G'''
 
| Mali-G78 <br>MP24
 
| Mali-G78 <br>MP24
 
| 759&nbsp;MHz <br>(1165.8 <br>GFLOPS <br>in FP32)
 
| 759&nbsp;MHz <br>(1165.8 <br>GFLOPS <br>in FP32)
Line 76: Line 95:
 
|}
 
|}
  
−
=== Kirin 9000S, 9010, 9020 series===
+
=== [[Kirin]] 9000S, 9010, 9020 series===
−
The Kirin 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 (Hi36A0) family are the first [[HiSilicon]]-developed  
+
The [[Kirin]] 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 (Hi36A0) family are the first [[HiSilicon]]-developed SoCs manufactured
−
:SoCs manufactured in high volumes in mainland China by [[Semiconductor Manufacturing International Corporation|SMIC]].  
+
:in high volumes in mainland China by ''Semiconductor Manufacturing International Corporation'' ([[SMIC]]).
 +
The SoCs are based on [[SMIC]]'s [[7 nm process|7 nm]] technology node, referred to as "N+2".
 +
:It also includes 1x Da Vinci "big" NPU core and 1x Da Vinci "small" NPU core.  
 
<!--
 
<!--
−
The SoC had its debut with the [[Huawei Mate 60]] in late 2023 with the Kirin 9000S alongside overclocked enhancements of the Kirin 9000S1 and Kirin 9010 with the Huawei Pura 70 series in early 2024.
+
The SoC had its debut with the Huawei Mate 60 in late 2023 with the Kirin 9000S alongside overclocked enhancements of the Kirin 9000S1 and Kirin 9010 with the Huawei Pura 70 series in early 2024.
 
According to Tom's Hardware, the Taishan V120 core, developed by HiSilicon, was roughly on par with AMD's Zen 3 cores from late 2020. Four of these cores were used in the 9000 series alongside four efficiency-focused [[Cortex-A510]] cores.
 
According to Tom's Hardware, the Taishan V120 core, developed by HiSilicon, was roughly on par with AMD's Zen 3 cores from late 2020. Four of these cores were used in the 9000 series alongside four efficiency-focused [[Cortex-A510]] cores.
−
The SoCs are based on SMIC's [[7 nm process|7 nm]] technology node, referred to as "N+2". It also includes 1 Da Vinci "big" NPU core and 1 Da Vinci "small" NPU core. Kirin 9000W, a Wi-Fi only SoC for the Huawei MatePad Pro 13.2 Wi-Fi only model, debuted in global markets in Q1 2024. The Kirin 9010 and Kirin 9000S1 debuted in Q2 2024, using a modified 2+6+4 core configuration with a new large Taishan core with the same configurations of medium and small cores from the Kirin 9000S with faster enhancements over the Kirin 9000S. -->
+
The SoCs are based on [[SMIC]]'s [[7 nm process|7 nm]] technology node, referred to as "N+2". It also includes 1 Da Vinci "big" NPU core and 1 Da Vinci "small" NPU core. Kirin 9000W, a Wi-Fi only SoC for the Huawei MatePad Pro 13.2 Wi-Fi only model, debuted in global markets in Q1 2024. The Kirin 9010 and Kirin 9000S1 debuted in Q2 2024, using a modified 2+6+4 core configuration with a new large Taishan core with the same configurations of medium and small cores from the Kirin 9000S with faster enhancements over the Kirin 9000S. -->
  
 
{| class="wikitable"
 
{| class="wikitable"
Line 103: Line 124:
 
! Band width <br>(GB/s)
 
! Band width <br>(GB/s)
 
|-
 
|-
−
| Kirin 9000S <br>(Hi36A0V120)
+
| '''Kirin 9000S''' <br>(Hi36A0V120)
−
| rowspan="17" | [[SMIC]] <br>[[7 nm]] <br>[[FinFET]]
+
| rowspan="17" | [[SMIC]] <br>''N+2'' <br>[[7 nm]] <br>[[FinFET]]
 
| rowspan="17" | [[ARMv8]].x
 
| rowspan="17" | [[ARMv8]].x
−
| rowspan="15" | [[HiSilicon]] <br>Taishan, <br>[[Cortex-A510]]
+
| rowspan="15" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}, <br>[[Cortex-A510]]
 
| rowspan="7"| 1+3+4 (8)<hr>2+6+4 (12)
 
| rowspan="7"| 1+3+4 (8)<hr>2+6+4 (12)
 
| 2.62 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| 2.62 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
−
| rowspan="15" | [[HiSilicon]] <br>Maleoon <br>910
+
| rowspan="15" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>910
 
| rowspan="15" | 750 <br>MHz
 
| rowspan="15" | 750 <br>MHz
 
| rowspan="17" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
 
| rowspan="17" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
Line 116: Line 137:
 
| Q3 2023
 
| Q3 2023
 
|-
 
|-
−
| Kirin 9000S1 <br>(Hi36A0V120)
+
| '''Kirin 9000S1''' <br>(Hi36A0V120)
 
| rowspan="6"| 2.49 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| rowspan="6"| 2.49 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| Q1 2024
 
| Q1 2024
 
|-
 
|-
−
| Kirin 9000W <br>(Hi36A0V120)
+
| '''Kirin 9000W''' <br>(Hi36A0V120)
 
| Q4 2023
 
| Q4 2023
 
|-
 
|-
−
| Kirin 9000WL <br>(Hi36A0V120)
+
| '''Kirin 9000WL''' <br>(Hi36A0V120)
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
−
| Kirin 9000WE <br>(Hi36A0V120)
+
| '''Kirin 9000WE''' <br>(Hi36A0V120)
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
−
| Kirin T90 <br>(Hi36A0V120)
+
| '''Kirin T90''' <br>(Hi36A0V120)
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin T90A <br>(Hi36A0V120)
+
| '''Kirin T90A''' <br>(Hi36A0V120)
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin 9000SL <br>(Hi36A0V120)
+
| '''Kirin 9000SL''' <br>(Hi36A0V120)
 
| rowspan="2"| 1+2+3 (6)<hr>2+4+3 (9)
 
| rowspan="2"| 1+2+3 (6)<hr>2+4+3 (9)
 
| rowspan="2"| 2.35 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| rowspan="2"| 2.35 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| Q4 2023
 
| Q4 2023
 
|-
 
|-
−
| Kirin 9000WM <br>(Hi36A0V120)
+
| '''Kirin 9000WM''' <br>(Hi36A0V120)
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
−
| Kirin 9010 <br>(Hi36A0V121)
+
| '''Kirin 9010''' <br>(Hi36A0V121)
 
| rowspan="5"| 1+3+4 (8) <hr>2+6+4 (12)
 
| rowspan="5"| 1+3+4 (8) <hr>2+6+4 (12)
 
| 2.30 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| 2.30 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
−
| Kirin 9010E <br>(Hi36A0V121)
+
| '''Kirin 9010E''' <br>(Hi36A0V121)
 
| rowspan="4"| 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| rowspan="4"| 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin 9010A <br>(Hi36A0V121)
+
| '''Kirin 9010A''' <br>(Hi36A0V121)
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin 9010W <br>(Hi36A0V121)
+
| '''Kirin 9010W''' <br>(Hi36A0V121)
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin T91 <br>(Hi36A0V121)
+
| '''Kirin T91''' <br>(Hi36A0V121)
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
−
| Kirin 9010L <br>(Hi36A0V121)
+
| '''Kirin 9010L''' <br>(Hi36A0V121)
 
| 1+2+3 (6) <hr>2+4+3 (9)
 
| 1+2+3 (6) <hr>2+4+3 (9)
 
| 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.40 GHz <br>([[Cortex-A510]])
 
| 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.40 GHz <br>([[Cortex-A510]])
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
−
| Kirin 9020 <br>(Hi36C0V110)
+
| '''Kirin 9020''' <br>(Hi36C0V110)
−
| rowspan="2" | [[HiSilicon]] <br>Taishan
+
| rowspan="2" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}
 
| rowspan="2" | 1+3+4 (8) <hr>2+6+4 (12)
 
| rowspan="2" | 1+3+4 (8) <hr>2+6+4 (12)
 
| rowspan="2" | 2.50 GHz <br>(TaishanV123)<br>2.15 GHz <br>(TaishanV120)<br>1.60 GHz <br>(Taishan-Little)
 
| rowspan="2" | 2.50 GHz <br>(TaishanV123)<br>2.15 GHz <br>(TaishanV120)<br>1.60 GHz <br>(Taishan-Little)
−
| rowspan="2" | [[HiSilicon]] <br>Maleoon <br>920
+
| rowspan="2" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>920
 
| rowspan="2" | 840 <br>MHz
 
| rowspan="2" | 840 <br>MHz
 
| Q4 2024
 
| Q4 2024
 
|-
 
|-
−
| Kirin T92 <br>(Hi36C0V110)
+
| '''Kirin T92''' <br>(Hi36C0V110)
 
| Q4 2024
 
| Q4 2024
 
|-
 
|-
 
|}
 
|}
 +
 +
== Server processors ==
 +
[[HiSilicon]] develops server processor SoCs based on the ARM architecture.
 +
 +
=== [[Hi1610]] ===
 +
The [[Hi1610]] is [[HiSilicon]]'s first generation server processor announced in [[2015]].
 +
:It features:
 +
* 16x ARM [[Cortex-A57]] @ 2.1GHz cores
 +
* 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 16MB CCN L3
 +
* [[TSMC]] [[16 nm]] process
 +
* 2x DDR4-1866 memory
 +
* 16x PCIe 3.0 ports
 +
 +
=== [[Hi1612]] ===
 +
The [[Hi1612]] is [[HiSilicon]]'s second generation server processor launched in [[2016]].
 +
:It is the first chiplet-based [[Kunpeng]] with two computing dies. It features:
 +
* 32x [[ARM]] [[Cortex-A57]] @ 2.1GHz cores
 +
* 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
 +
* [[TSMC]] [[16 nm]] process
 +
* 4x DDR4-2133 memory
 +
* 16x PCIe 3.0 ports
 +
 +
=== Kunpeng 916 ([[Hi1616]]) ===
 +
The [[Kunpeng 916]] ([[Hi1616]]) is [[HiSilicon]]'s third generation server processor launched in [[2017]].
 +
:The Kunpeng 916 is used in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server,
 +
:TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server. It features:
 +
* 32x [[ARM]] [[Cortex-A72]] @ 2.4GHz cores
 +
* 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
 +
* [[TSMC]] [[16 nm]] process
 +
* 4x DDR4-2400 memory
 +
* 2-way SMP, Each socket has 2x ports with
 +
: 96 Gbit/s per port (total of 192 Gbit/s)
 +
* 46x PCIe 3.0 and 8x 10G Ethernet ports
 +
* 85 W [[TBD]]
 +
 +
=== Kunpeng 920 ([[Hi1620]]) ===
 +
The [[Kunpeng 920]] ([[Hi1620]]) is [[HiSilicon]]'s fourth generation server processor
 +
:announced in [[2018]], and launched in 2019. <!--
 +
:Huawei claims the Kunpeng 920 CPU scores more than an estimated 930 on SPECint_rate_base2006.
 +
:The Kunpeng 920 is used in Huawei's TaiShan 2280 V2 Balanced Server,
 +
:TaiShan 5280 V2 Storage Server, and TaiShan XA320 V2 High-Density Server Node. --> It features:
 +
* 32 to 64x custom TaiShan V110 cores @ 2.6GHz cores <ref>{{cite book |url=https://fuse.wikichip.org/news/2274/huawei-expands-kunpeng-server-cpus-plans-smt-sve-for-next-gen/ |title=Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen |last=Schor |first=David |date=3 May 2019 |website=WikiChip Fuse}}</ref>
 +
* The TaiShan V110 core is a 4-way superscalar, out-of-order
 +
:microarchitecture that implements the [[ARMv8]].2-A ISA. <!-- Huawei reports the core supports almost all
 +
:the ARMv8.4-A ISA features with a few exceptions, including the [[dot product]] and FP16 FML extensions.-->
 +
* The TaiShan V110 cores are likely a new core not based on ARM designs
 +
* 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3),
 +
: 2x FSUs (ASIMD FPU), 2x LSUs
 +
* 64KB L1-I, 64KB L1-D, 512KB Private L2, 1MB L3/core (shared)
 +
* [[TSMC]] [[7 nm]] HPC process
 +
* 8x DDR4-3200 memory
 +
* 2-way and 4-way SMP, Each socket has 3x Hydra ports
 +
: with 240 Gbit/s per port (total of 720 Gbit/s)
 +
* 40x PCIe 4.0 with CCIX support, 4x USB 3.0, 2x SATA 3.0,
 +
: 8x SAS 3.0 and 2x 100G Ethernet ports
 +
* [[TBD]] 100 to 200 W
 +
* Compression engine (GZIP, LZS, LZ4) capable of up
 +
: to 40 Git/s compress and 100 Gbit/s decompress
 +
* Crypto offload engine (for AES, DES, 3DES, SHA1/2)
 +
: capable of throughputs up to 100 Gbit/s
 +
 +
=== Kunpeng 930 ([[Hi1630]]) ===
 +
The [[Kunpeng 930]] ([[Hi1630]]) is [[HiSilicon]]'s fifth-generation server processor
 +
:announced in [[2019]] and scheduled for launch in [[2021]]. It features:
 +
* 80 custom Taishan V120 cores @ 3GHz frequency, with support
 +
: for SMT and ARM's Scalable Vector Extension (SVE)
 +
* 64KB L1-I, 64KB L1-D, 512KB Private L2 and 1MB L3/core (shared)
 +
* [[TSMC]] [[5 nm]] process
 +
* 8x DDR5 memory
 +
 +
=== Kunpeng 950 ===
 +
The [[Kunpeng 950]] is [[HiSilicon]]'s sixth-generation server processor
 +
:announced in [[2019]] and scheduled for launch in [[2023]].
 +
 +
== References ==

Revision as of 18:31, 27 March 2025


HiSilicon

Family

Kirin
TaiShan (uarch)

Kirin 9000E, 9000L, 9000 5G/4G series

Kirin 9000 is HiSilicon's first SoC based on 5 nm+ FinFET (EUV) TSMC technology (N5 node)

and the first 5 nm SoC to be launched on the international market. [1]

This octa-core system on a chip is based on the 9th Gen of the HiSilicon Kirin series

and is equipped with 15.3 billion transistors in a 1+3+4 core configuration:
  • 4x ARM Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz),
  • 4x ARM Cortex-A55 (4x 2.05 GHz) and
  • 24-core Mali-G78 GPU (22-core in the Kirin 9000E version)

The Kirin 9000L uses a 1+2+3 core configuration:

  • 3x ARM Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz),
  • 3x ARM Cortex-A55 (3x 2.05 GHz) and
  • 22-core Mali-G78 GPU with Kirin Gaming + 3.0 implementation
Spec
  • GPU
    • Kirin 9000L: ARM Mali-G78 MP22
    • Kirin 9000E: ARM Mali-G78 MP22
    • Kirin 9000: ARM Mali-G78 MP24
  • Da Vinci NPU architecture 2.0
    • Kirin 9000L: 1x Big Core + 1x Tiny Core
    • Kirin 9000E: 1x Big Core + 1x Tiny Core
    • Kirin 9000: 2x Big Cores + 1x Tiny Core
Model number Fab node CPU GPU Memory technology Sampling
availability
ISA µarch Cores Freq (GHz) µarch Freq
(MHz) 		Type Bus width
(bit) 		Band width
(GB/s)
Kirin 9000L TSMC 5 nm+
FinFET (EUV) 		ARM
v8.2-A 		Cortex-A77
Cortex-A55
(big.LITTLE) 		(1+2)+3 3.13 (A77 H)
2.54 (A77 L)
2.05 (A55) 		Mali-G78
MP22 		759 MHz
(1068.7
GFLOPS
in FP32) 		LPDDR4X
-2133
LPDDR5
-2750 		64-bit (4x16-bit)
Quad-channel 		LPDDR4X
(34.1 GB/s)
LPDDR5
(44.0 GB/s) 		Q4 2020
Kirin 9000E (1+3)+4
Kirin 9000
(Hi36A0V101)
Kirin 9000 4G
Kirin 9000 5G 		Mali-G78
MP24 		759 MHz
(1165.8
GFLOPS
in FP32)

Kirin 9000S, 9010, 9020 series

The Kirin 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 (Hi36A0) family are the first HiSilicon-developed SoCs manufactured

in high volumes in mainland China by Semiconductor Manufacturing International Corporation (SMIC).

The SoCs are based on SMIC's 7 nm technology node, referred to as "N+2".

It also includes 1x Da Vinci "big" NPU core and 1x Da Vinci "small" NPU core.
Model number Fab node CPU GPU Memory technology Sampling
availability
ISA µarch Cores (total)
Threads (total) 		Freq (GHz) µarch Freq
(MHz) 		Type Bus width
(bit) 		Band width
(GB/s)
Kirin 9000S
(Hi36A0V120) 		SMIC
N+2
7 nm
FinFET 		ARMv8.x HiSilicon
TaiShan,
Cortex-A510 		1+3+4 (8)
2+6+4 (12) 		2.62 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		HiSilicon
Maleoon
910 		750
MHz 		LPDDR5
-6400
LPDDR5X
-8533 		64-bit
(4x16-bit)
Quad-
channel 		LPDDR5
(51.2 MB/s)
LPDDR5X
(68.2 MB/s) 		Q3 2023
Kirin 9000S1
(Hi36A0V120) 		2.49 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		Q1 2024
Kirin 9000W
(Hi36A0V120) 		Q4 2023
Kirin 9000WL
(Hi36A0V120) 		Q2 2024
Kirin 9000WE
(Hi36A0V120) 		Q2 2024
Kirin T90
(Hi36A0V120) 		Q3 2024
Kirin T90A
(Hi36A0V120) 		Q3 2024
Kirin 9000SL
(Hi36A0V120) 		1+2+3 (6)
2+4+3 (9) 		2.35 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		Q4 2023
Kirin 9000WM
(Hi36A0V120) 		Q2 2024
Kirin 9010
(Hi36A0V121) 		1+3+4 (8)
2+6+4 (12) 		2.30 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.55 GHz
(Cortex-A510) 		Q2 2024
Kirin 9010E
(Hi36A0V121) 		2.19 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.55 GHz
(Cortex-A510) 		Q3 2024
Kirin 9010A
(Hi36A0V121) 		Q3 2024
Kirin 9010W
(Hi36A0V121) 		Q3 2024
Kirin T91
(Hi36A0V121) 		Q3 2024
Kirin 9010L
(Hi36A0V121) 		1+2+3 (6)
2+4+3 (9) 		2.19 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.40 GHz
(Cortex-A510) 		Q2 2024
Kirin 9020
(Hi36C0V110) 		HiSilicon
TaiShan 		1+3+4 (8)
2+6+4 (12) 		2.50 GHz
(TaishanV123)
2.15 GHz
(TaishanV120)
1.60 GHz
(Taishan-Little) 		HiSilicon
Maleoon
920 		840
MHz 		Q4 2024
Kirin T92
(Hi36C0V110) 		Q4 2024

Server processors

HiSilicon develops server processor SoCs based on the ARM architecture.

Hi1610

The Hi1610 is HiSilicon's first generation server processor announced in 2015.

It features:
  • 16x ARM Cortex-A57 @ 2.1GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 16MB CCN L3
  • TSMC 16 nm process
  • 2x DDR4-1866 memory
  • 16x PCIe 3.0 ports

Hi1612

The Hi1612 is HiSilicon's second generation server processor launched in 2016.

It is the first chiplet-based Kunpeng with two computing dies. It features:
  • 32x ARM Cortex-A57 @ 2.1GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
  • TSMC 16 nm process
  • 4x DDR4-2133 memory
  • 16x PCIe 3.0 ports

Kunpeng 916 (Hi1616)

The Kunpeng 916 (Hi1616) is HiSilicon's third generation server processor launched in 2017.

The Kunpeng 916 is used in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server,
TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server. It features:
  • 32x ARM Cortex-A72 @ 2.4GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
  • TSMC 16 nm process
  • 4x DDR4-2400 memory
  • 2-way SMP, Each socket has 2x ports with
96 Gbit/s per port (total of 192 Gbit/s)
  • 46x PCIe 3.0 and 8x 10G Ethernet ports
  • 85 W TBD

Kunpeng 920 (Hi1620)

The Kunpeng 920 (Hi1620) is HiSilicon's fourth generation server processor

announced in 2018, and launched in 2019. It features:
  • 32 to 64x custom TaiShan V110 cores @ 2.6GHz cores [2]
  • The TaiShan V110 core is a 4-way superscalar, out-of-order
microarchitecture that implements the ARMv8.2-A ISA.
  • The TaiShan V110 cores are likely a new core not based on ARM designs
  • 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3),
2x FSUs (ASIMD FPU), 2x LSUs
  • 64KB L1-I, 64KB L1-D, 512KB Private L2, 1MB L3/core (shared)
  • TSMC 7 nm HPC process
  • 8x DDR4-3200 memory
  • 2-way and 4-way SMP, Each socket has 3x Hydra ports
with 240 Gbit/s per port (total of 720 Gbit/s)
  • 40x PCIe 4.0 with CCIX support, 4x USB 3.0, 2x SATA 3.0,
8x SAS 3.0 and 2x 100G Ethernet ports
  • TBD 100 to 200 W
  • Compression engine (GZIP, LZS, LZ4) capable of up
to 40 Git/s compress and 100 Gbit/s decompress
  • Crypto offload engine (for AES, DES, 3DES, SHA1/2)
capable of throughputs up to 100 Gbit/s

Kunpeng 930 (Hi1630)

The Kunpeng 930 (Hi1630) is HiSilicon's fifth-generation server processor

announced in 2019 and scheduled for launch in 2021. It features:
  • 80 custom Taishan V120 cores @ 3GHz frequency, with support
for SMT and ARM's Scalable Vector Extension (SVE)
  • 64KB L1-I, 64KB L1-D, 512KB Private L2 and 1MB L3/core (shared)
  • TSMC 5 nm process
  • 8x DDR5 memory

Kunpeng 950

The Kunpeng 950 is HiSilicon's sixth-generation server processor

announced in 2019 and scheduled for launch in 2023.

References

  1. ↑ (16 September 2021) Kirin 9000.
  2. ↑ Schor, David (3 May 2019). Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen.
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