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Difference between revisions of "amd/epyc/7352"
(Added missing data. Changed base & turbo freq as specified in datasheet & on AMD website.) |
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|model number=7352 | |model number=7352 | ||
|part number=100-000000077 | |part number=100-000000077 | ||
| + | |part number 2=100-100000077WOF | ||
|market=Server | |market=Server | ||
|first announced=August 7, 2019 | |first announced=August 7, 2019 | ||
|first launched=August 7, 2019 | |first launched=August 7, 2019 | ||
| + | |release price=$1350.00 | ||
|family=EPYC | |family=EPYC | ||
|series=7002 | |series=7002 | ||
|locked=Yes | |locked=Yes | ||
| − | |frequency=2, | + | |frequency=2,300 MHz |
| − | |turbo frequency=3, | + | |turbo frequency=3,200 MHz |
| − | |clock multiplier= | + | |clock multiplier=23 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
| Line 22: | Line 24: | ||
|core name=Rome | |core name=Rome | ||
|core family=23 | |core family=23 | ||
| + | |core model=49 | ||
| + | |core stepping=B0 | ||
|process=7 nm | |process=7 nm | ||
|process 2=14 nm | |process 2=14 nm | ||
| Line 37: | Line 41: | ||
|predecessor link=amd/epyc/7351 | |predecessor link=amd/epyc/7351 | ||
}} | }} | ||
| − | '''EPYC 7352''' is a {{arch|64}} [[tetracosa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7352 has a TDP of 155 W with a base frequency of 2. | + | '''EPYC 7352''' is a {{arch|64}} [[tetracosa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7352 has a TDP of 155 W with a base frequency of 2.3 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket. |
== Cache == | == Cache == | ||
| Line 49: | Line 53: | ||
|l1d break=24x32 KiB | |l1d break=24x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| + | |l1d policy=write-back | ||
|l2 cache=12 MiB | |l2 cache=12 MiB | ||
|l2 break=24x512 KiB | |l2 break=24x512 KiB | ||
| Line 84: | Line 89: | ||
}} | }} | ||
| − | == Features == | + | == Features == |
{{x86 features | {{x86 features | ||
|real=Yes | |real=Yes | ||
| Line 193: | Line 198: | ||
|amdpbod=No | |amdpbod=No | ||
}} | }} | ||
| + | |||
| + | == References == | ||
| + | * [https://www.amd.com/en/products/cpu/amd-epyc-7352 "AMD EPYC™ 7352"]. <i>AMD.com</i>. Retrieved October 2020. | ||
| + | * [https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020 | ||
Latest revision as of 18:26, 9 January 2021
| Edit Values | |
| EPYC 7352 | |
| General Info | |
| Designer | AMD |
| Manufacturer | TSMC, GlobalFoundries |
| Model Number | 7352 |
| Part Number | 100-000000077, 100-100000077WOF |
| Market | Server |
| Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
| Release Price | $1350.00 |
| Shop | Amazon |
| General Specs | |
| Family | EPYC |
| Series | 7002 |
| Locked | Yes |
| Frequency | 2,300 MHz |
| Turbo Frequency | 3,200 MHz |
| Clock multiplier | 23 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Zen 2 |
| Core Name | Rome |
| Core Family | 23 |
| Core Model | 49 |
| Core Stepping | B0 |
| Process | 7 nm, 14 nm |
| Technology | CMOS |
| MCP | Yes (5 dies) |
| Word Size | 64 bit |
| Cores | 24 |
| Threads | 48 |
| Max Memory | 4 TiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Electrical | |
| TDP | 155 W |
| Packaging | |
| Package | SP3, FCLGA-4094 (FC-OLGA) |
| Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
| Pitch | 0.87 mm × 1 mm |
| Contacts | 4094 |
| Socket | SP3, LGA-4094 |
| Succession | |
EPYC 7352 is a 64-bit tetracosa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7352 has a TDP of 155 W with a base frequency of 2.3 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.
Cache[edit]
- Main article: Zen 2 § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
References[edit]
- "AMD EPYC™ 7352". AMD.com. Retrieved October 2020.
- "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
Facts about "EPYC 7352 - AMD"
| base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
| clock multiplier | 24 + |
| core count | 24 + |
| core family | 23 + |
| core name | Rome + |
| designer | AMD + |
| die count | 5 + |
| family | EPYC + |
| first announced | August 7, 2019 + |
| first launched | August 7, 2019 + |
| full page name | amd/epyc/7352 + |
| has ecc memory support | true + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| is multi-chip package | true + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
| l3$ size | 128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) + |
| ldate | August 7, 2019 + |
| manufacturer | TSMC + and GlobalFoundries + |
| market segment | Server + |
| max cpu count | 2 + |
| max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
| max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
| max memory channels | 8 + |
| microarchitecture | Zen 2 + |
| model number | 7352 + |
| name | EPYC 7352 + |
| package | SP3 + and FCLGA-4094 + |
| part number | 100-000000077 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
| series | 7002 + |
| smp max ways | 2 + |
| socket | SP3 + and LGA-4094 + |
| supported memory type | DDR4-3200 + |
| tdp | 155 W (155,000 mW, 0.208 hp, 0.155 kW) + |
| technology | CMOS + |
| thread count | 48 + |
| turbo frequency | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |