(Fixed part number. Changed base freq as specified in datasheet & on AMD website.) |
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|model number=7272 | |model number=7272 | ||
|part number=100-000000079 | |part number=100-000000079 | ||
+ | |part number 2=100-100000079WOF | ||
|market=Server | |market=Server | ||
|first announced=August 7, 2019 | |first announced=August 7, 2019 | ||
|first launched=August 7, 2019 | |first launched=August 7, 2019 | ||
+ | |release price (tray)=$625.00 | ||
|family=EPYC | |family=EPYC | ||
|series=7002 | |series=7002 | ||
|locked=Yes | |locked=Yes | ||
− | |frequency=2, | + | |frequency=2,900 MHz |
|turbo frequency=3,200 MHz | |turbo frequency=3,200 MHz | ||
− | |clock multiplier= | + | |clock multiplier=29 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 22: | Line 24: | ||
|core name=Rome | |core name=Rome | ||
|core family=23 | |core family=23 | ||
+ | |core model=49 | ||
+ | |core stepping=B0 | ||
|process=7 nm | |process=7 nm | ||
|process 2=14 nm | |process 2=14 nm | ||
Line 35: | Line 39: | ||
|package name 1=amd,socket_sp3 | |package name 1=amd,socket_sp3 | ||
}} | }} | ||
− | '''EPYC 7272''' is a {{arch|64}} [[dodeca-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates | + | '''EPYC 7272''' is a {{arch|64}} [[dodeca-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on a [[GlobalFoundries]] [[14 nm process]]. The 7272 has a TDP of 120 W with a base frequency of 2.9 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of memory per socket. |
== Cache == | == Cache == | ||
Line 47: | Line 51: | ||
|l1d break=12x32 KiB | |l1d break=12x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
|l2 cache=6 MiB | |l2 cache=6 MiB | ||
|l2 break=12x512 KiB | |l2 break=12x512 KiB | ||
Line 56: | Line 61: | ||
== Memory controller == | == Memory controller == | ||
+ | This model supports up to 8 channels of up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7272 "AMD EPYC™ 7272"]. <i>AMD.com</i>. Retrieved October 2020.</ref><ref name="datasheet">[https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020</ref> with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the [[amd/infinity_fabric|IFOP]] links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK<ref name="isscc2020j-chiplet">Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:[https://doi.org/10.1109/ISSCC19947.2020.9063103 10.1109/ISSCC19947.2020.9063103]</ref>). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).<ref name="datasheet"/> | ||
+ | |||
{{memory controller | {{memory controller | ||
|type=DDR4-3200 | |type=DDR4-3200 | ||
Line 82: | Line 89: | ||
}} | }} | ||
− | == Features == | + | == Features == |
{{x86 features | {{x86 features | ||
|real=Yes | |real=Yes | ||
Line 191: | Line 198: | ||
|amdpbod=No | |amdpbod=No | ||
}} | }} | ||
+ | |||
+ | == References == | ||
+ | <references/> |
Latest revision as of 19:35, 9 January 2021
Edit Values | |
EPYC 7272 | |
General Info | |
Designer | AMD |
Manufacturer | TSMC, GlobalFoundries |
Model Number | 7272 |
Part Number | 100-000000079, 100-100000079WOF |
Market | Server |
Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
Release Price | $625.00 (tray) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7002 |
Locked | Yes |
Frequency | 2,900 MHz |
Turbo Frequency | 3,200 MHz |
Clock multiplier | 29 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 2 |
Core Name | Rome |
Core Family | 23 |
Core Model | 49 |
Core Stepping | B0 |
Process | 7 nm, 14 nm |
Technology | CMOS |
MCP | Yes (3 dies) |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 4 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 120 W |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7272 is a 64-bit dodeca-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates two compute dies fabricated on a TSMC 7 nm process and an I/O die fabricated on a GlobalFoundries 14 nm process. The 7272 has a TDP of 120 W with a base frequency of 2.9 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of memory per socket.
Cache[edit]
- Main article: Zen 2 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
This model supports up to 8 channels of up to DDR4-3200 memory[1][2] with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the IFOP links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK[3]). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).[2]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
References[edit]
- ↑ "AMD EPYC™ 7272". AMD.com. Retrieved October 2020.
- ↑ 2.0 2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
- ↑ Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
clock multiplier | 26 + |
core count | 12 + |
core family | 23 + |
core name | Rome + |
designer | AMD + |
die count | 3 + |
family | EPYC + |
first announced | August 7, 2019 + |
first launched | August 7, 2019 + |
full page name | amd/epyc/7272 + |
has ecc memory support | true + |
has locked clock multiplier | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | August 7, 2019 + |
manufacturer | TSMC + and GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
max memory channels | 8 + |
microarchitecture | Zen 2 + |
model number | 7272 + |
name | EPYC 7272 + |
package | SP3 + and FCLGA-4094 + |
part number | 100-000000079 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 7002 + |
smp max ways | 2 + |
socket | SP3 + and LGA-4094 + |
supported memory type | DDR4-3200 + |
tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
technology | CMOS + |
thread count | 24 + |
turbo frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |