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Difference between revisions of "intel/xeon bronze/3204"
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{{chip
 
{{chip
 
|name=Xeon Bronze 3204
 
|name=Xeon Bronze 3204
−
|image=skylake sp (basic).png
+
|image=cascade lake sp (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=3204
 
|model number=3204
 +
|part number=CD8069503956700
 +
|s-spec=SRFBP
 
|market=Server
 
|market=Server
 
|market 2=Workstation
 
|market 2=Workstation
−
|first announced=2019
+
|market 3=Embedded
−
|first launched=2019
+
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|release price (tray)=$213.00
 +
|release price (box)=$224.00
 
|family=Xeon Bronze
 
|family=Xeon Bronze
−
|series=3000
+
|series=3200
 
|locked=Yes
 
|locked=Yes
 
|frequency=1,900 MHz
 
|frequency=1,900 MHz
Line 22: Line 27:
 
|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
 +
|core stepping=R1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 28: Line 34:
 
|thread count=6
 
|thread count=6
 
|max cpus=2
 
|max cpus=2
 +
|max memory=1 TiB
 
|tdp=85 W
 
|tdp=85 W
 
|tcase min=0 °C
 
|tcase min=0 °C
−
|tcase max=78 °C
+
|tcase max=77 °C
−
|package module 1={{packages/intel/fclga-3647}}
+
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Bronze 3104
 +
|predecessor link=intel/xeon bronze/3104
 
}}
 
}}
−
'''Xeon Bronze 3204''' is a {{arch|64}} [[hexa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor set to be introduced by [[Intel]] in early 2019. The Bronze 3204, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.9 GHz with a TDP of 85 W, supports up ? GiB of hexa-channel DDR4-2133 ECC memory.
+
'''Xeon Bronze 3204''' is a {{arch|64}} [[hexa-core]] [[x86]] entry-level server microprocessor introduced by [[Intel]] in early [[2019]]. The Bronze 3204 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports a single {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2133 memory, operates at 1.9 GHz with a TDP of 150 W.
  
 
== Cache ==
 
== Cache ==
Line 60: Line 69:
 
|type=DDR4-2133
 
|type=DDR4-2133
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=768 GiB
+
|max mem=1 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
Line 110: Line 119:
 
|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
 +
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
Line 125: Line 135:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=No
 
|tbt2=No
Line 134: Line 145:
 
|fastmem=No
 
|fastmem=No
 
|ivmd=Yes
 
|ivmd=Yes
 +
|intelnodecontroller=No
 
|intelnode=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|kpt=Yes
 
|ptt=Yes
 
|ptt=Yes
 +
|intelrunsure=No
 
|mbe=Yes
 
|mbe=Yes
 
|isrt=No
 
|isrt=No
Line 155: Line 168:
 
|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 168: Line 183:
 
|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=1,900MHz
 +
|freq_1=1,900MHz
 +
|freq_2=1,900MHz
 +
|freq_3=1,900MHz
 +
|freq_4=1,900MHz
 +
|freq_5=1,900MHz
 +
|freq_6=1,900MHz
 +
|freq_avx2_base=1,500MHz
 +
|freq_avx2_1=1,500MHz
 +
|freq_avx2_2=1,500MHz
 +
|freq_avx2_3=1,500MHz
 +
|freq_avx2_4=1,500MHz
 +
|freq_avx2_5=1,500MHz
 +
|freq_avx2_6=1,500MHz
 +
|freq_avx512_base=1,000MHz
 +
|freq_avx512_1=1,000MHz
 +
|freq_avx512_2=1,000MHz
 +
|freq_avx512_3=1,000MHz
 +
|freq_avx512_4=1,000MHz
 +
|freq_avx512_5=1,000MHz
 +
|freq_avx512_6=1,000MHz
 
}}
 
}}

Latest revision as of 09:31, 8 May 2019

Edit Values
Xeon Bronze 3204
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number3204
Part NumberCD8069503956700
S-SpecSRFBP
MarketServer, Workstation, Embedded
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$213.00 (tray)
$224.00 (box)
ShopAmazon
General Specs
FamilyXeon Bronze
Series3200
LockedYes
Frequency1,900 MHz
Clock multiplier19
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingR1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores6
Threads6
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP85 W
Tcase0 °C – 77 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Bronze 3204 is a 64-bit hexa-core x86 entry-level server microprocessor introduced by Intel in early 2019. The Bronze 3204 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports a single AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2133 memory, operates at 1.9 GHz with a TDP of 150 W.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  6x1 MiB16-way set associativewrite-back
L3$8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
  6x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth95.37 GiB/s
97,658.88 MiB/s
102.403 GB/s
102,402.758 MB/s
0.0931 TiB/s
0.102 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/s
Hexa 95.37 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456
Normal1,900MHz1,900MHz1,900MHz1,900MHz1,900MHz1,900MHz1,900MHz
AVX21,500MHz1,500MHz1,500MHz1,500MHz1,500MHz1,500MHz1,500MHz
AVX5121,000MHz1,000MHz1,000MHz1,000MHz1,000MHz1,000MHz1,000MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_bronze/3204&oldid=90439"
Facts about "Xeon Bronze 3204 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Bronze 3204 - Intel#io +
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +
chipsetLewisburg +
clock multiplier19 +
core count6 +
core family6 +
core nameCascade Lake SP +
designerIntel +
familyXeon Bronze +
first announced2019 +
first launched2019 +
full page nameintel/xeon bronze/3204 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description16-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description11-way set associative +
l3$ size8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
ldate2019 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer + and Workstation +
max case temperature351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count2 +
max memory bandwidth95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number3204 +
nameXeon Bronze 3204 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series3000 +
smp max ways2 +
supported memory typeDDR4-2133 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count6 +
word size64 bit (8 octets, 16 nibbles) +