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Difference between revisions of "movidius/microarchitectures/shave v3.0"
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(Key changes from {{\\|SHAVE v2.0}})
 
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* [[28 nm process]] (from [[65 nm]])
 
* [[28 nm process]] (from [[65 nm]])
 
* 20-30x performance  
 
* 20-30x performance  
** 600 MHz (3.33x, from 180 MHz)
+
** 600 MHz (3.33x, from 180 MHz)
 
** 12 SHAVE cores (from 8)
 
** 12 SHAVE cores (from 8)
** 5x per-core performance improvement
+
** Various per-core performance improvement
 +
* 20 new hardware accelerators
 +
* Aggregate nominal 600 Mpixel/sec throughput
 
* [[LEON4]] [[SPARC]] core (from [[LEON3]])
 
* [[LEON4]] [[SPARC]] core (from [[LEON3]])
 
* Added support for [[OpenCL]]
 
* Added support for [[OpenCL]]
 +
 +
== Overview ==
 +
[[File:shave v3 overview.svg|right|400px]]
 +
 +
== Core ==
 +
{{empty section}}
 +
 +
== Package ==
 +
{{empty section}}
  
 
== Die ==
 
== Die ==

Latest revision as of 04:49, 16 March 2018

Edit Values
SHAVE v3.0 µarch
General Info
Arch TypeAccelerator
DesignerMovidius
ManufacturerTSMC
Introduction2014
Process28 nm
Pipeline
TypeVLLIW
Instructions
ISASHAVE, SPARC v8
Cache
L2 Cache256 KiB/chip
2-way set associative
Side Cache128-256 MiB SDRAM/chip
Succession

Fragrak or Streaming Hybrid Architecture Vector Engine v3.0 (SHAVE v3.0) is an accelerator microarchitecture designed by Movidius for their vision processors, serving as a successor to the SHAVE v2.0. SHAVE-based products are branded as the Myriad 2 family of vision processors.

History[edit]

The SHAVE v3.0 microarchitecture is based on the SHAVE v2.0 microarchitecture which Movidius disclosed in 2011. The architecture is a word of a 70-staff team consisting of 65 engineers - 10% working on hardware while the remaining 90% were working on the system tools and software design.

Process Technology[edit]

Main article: 28 nm lithography process

This microarchitecture was designed for TSMC's 28 nm process.

Architecture[edit]

Key changes from SHAVE v2.0[edit]

  • 28 nm process (from 65 nm)
  • 20-30x performance
    • 600 MHz (3.33x, from 180 MHz)
    • 12 SHAVE cores (from 8)
    • Various per-core performance improvement
  • 20 new hardware accelerators
  • Aggregate nominal 600 Mpixel/sec throughput
  • LEON4 SPARC core (from LEON3)
  • Added support for OpenCL

Overview[edit]

shave v3 overview.svg

Core[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Package[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]


myriad 2 (shave v3.0) die shot.png


myriad 2 (shave v3.0) die shot (annotated).png
codenameSHAVE v3.0 +
designerMovidius +
first launched2014 +
full page namemovidius/microarchitectures/shave v3.0 +
instance ofmicroarchitecture +
instruction set architectureSHAVE + and SPARC v8 +
manufacturerTSMC +
nameSHAVE v3.0 +
process28 nm (0.028 μm, 2.8e-5 mm) +