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{{movidius title|SABRE}}
 
{{movidius title|SABRE}}
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'''SABRE''' was a test microprocessor designed by [[Movidius]] for the [[acceleration]] of machine vision. The SABRE microprocessor eventually lead to the production definition of the {{movidius|Myriad|Myriad 1}} line of vision accelerators. SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a [[SPARC]] {{sparc|V8}} [[LEON3]] core and 8 additional {{movidius|SHAVE v2.0|l=arch}} cores.
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|name=SABRE
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|no image=Yes
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|designer=Movidius
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|manufacturer=TSMC
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|model number=SABRE
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|market=Embedded
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|market 2=Mobile
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|frequency=180 MHz
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|isa=SPARC V8
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|isa family=SPARC
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|isa 2=SHAVE
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|isa 2 family=SHAVE
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|microarch=LEON3
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|microarch 2=SHAVE v2.0
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|process=65 nm
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|technology=CMOS
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|word size=32 bit
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|core count=9
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|thread count=9
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}}
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'''SABRE''' was a test microprocessor designed by [[Movidius]] for the [[acceleration]] of machine vision. SABRE was a modification of the original {{\\|ISAAC}} designed back in 2007 as a game physics accelerator. The SABRE microprocessor eventually lead to the production definition of the {{movidius|Myriad|Myriad 1}} line of vision accelerators.
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== Overview ==
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SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a [[SPARC]] {{sparc|V8}} [[LEON3]] core and 8 additional {{movidius|SHAVE v2.0|l=arch}} cores.
  
 
The test platform consisted of a  [[Samsung]] 6410 [[daughtercard]] which incoluded an [[S3C6410X]] processor ([[ARM11]]) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.
 
The test platform consisted of a  [[Samsung]] 6410 [[daughtercard]] which incoluded an [[S3C6410X]] processor ([[ARM11]]) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.
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[[File:movidius sabre test board.png|500px]]
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== Block diagram ==
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:[[File:movidius sabre block diagram.png|500px]]
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== References ==
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* Tite, Teodor, et al. "moviOS: a Real-Time Multiprocessor Operating System for Multimedia Applications."
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* [https://www.movidius.com/news/happy-10th-birthday-movidius Happy 10th Birthday Movidius]

Latest revision as of 10:31, 11 March 2018

Edit Values
SABRE
General Info
DesignerMovidius
ManufacturerTSMC
Model NumberSABRE
MarketEmbedded, Mobile
General Specs
Frequency180 MHz
Microarchitecture
ISASPARC V8 (SPARC), SHAVE (SHAVE)
MicroarchitectureLEON3, SHAVE v2.0
Process65 nm
TechnologyCMOS
Word Size32 bit
Cores9
Threads9

SABRE was a test microprocessor designed by Movidius for the acceleration of machine vision. SABRE was a modification of the original ISAAC designed back in 2007 as a game physics accelerator. The SABRE microprocessor eventually lead to the production definition of the Myriad 1 line of vision accelerators.

Overview[edit]

SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a SPARC V8 LEON3 core and 8 additional SHAVE v2.0 cores.

The test platform consisted of a Samsung 6410 daughtercard which incoluded an S3C6410X processor (ARM11) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.

movidius sabre test board.png

Block diagram[edit]

movidius sabre block diagram.png

References[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=movidius/sabre&oldid=75091"
Facts about "SABRE - Intel Movidius"
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base frequency180 MHz (0.18 GHz, 180,000 kHz) +
core count9 +
designerMovidius +
full page namemovidius/sabre +
instance ofmicroprocessor +
isaSPARC V8 + and SHAVE +
isa familySPARC + and SHAVE +
ldate1900 +
manufacturerTSMC +
market segmentEmbedded + and Mobile +
microarchitectureLEON3 + and SHAVE v2.0 +
model numberSABRE +
nameSABRE +
process65 nm (0.065 μm, 6.5e-5 mm) +
technologyCMOS +
thread count9 +
word size32 bit (4 octets, 8 nibbles) +