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Difference between revisions of "movidius/myriad/ma1110"
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{{movidius title|Myriad 1 MA1110}}
 
{{movidius title|Myriad 1 MA1110}}
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{{chip}}
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{{chip
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|name=Myriad 1 MA1110
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|no image=Yes
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|designer=Movidius
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|manufacturer=TSMC
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|model number=MA1110
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|market=Embedded
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|market 2=Mobile
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|first announced=January 15, 2009
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|first launched=June, 2009
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|family=Myriad
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|series=1
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|frequency=180 MHz
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|isa=SPARC V8
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|isa family=SPARC
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|isa 2=SHAVE
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|isa 2 family=SHAVE
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|microarch=LEON3
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|microarch 2=SHAVE v2.0
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|process=65 nm
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|technology=TSMC
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|word size=32 bit
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|core count=9
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|thread count=9
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|v core=1.2 V
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|v io=2.5 V
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}}
 
'''Myriad 1 MA1110''' was a vision processing [[accelerator]] designed by [[Movidius]] and introduced in [[2009]].
 
'''Myriad 1 MA1110''' was a vision processing [[accelerator]] designed by [[Movidius]] and introduced in [[2009]].
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== Overview ==
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The MA1110 is a vision [[accelerator]] designed to work alongside a main host processors, typically in a mobile or embedded device. The MA1110 consists of a single [[SPARC]] {{sparc|V8}} [[LEON3]] core which is used for management and control and eight {{movidius|SHAVE v2.0|l=arch}} core which are the workhorse of this chip. Each core has 128 KiB of cache. The eight SHAVE cores together are capable of 20GFLOPS of processing power at just a few 100s milliwatt of power.
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[[File:movidius ma1000 silicon platform.png|600px]]
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== Extensions ==
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* Host Memory Bus (master and slave): 8-bit / 16-bit / 32-bit
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* Video Output Formats:
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** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
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** 24bpp, 16M colors, resolutions up to 2048x2048
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** Video support for 4 layers of video and graphics
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* External TV Support
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** Video Output to External HDMI Driver Chip
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* Multiple I2S (Master/Slave) stereo audio channels
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** Independent sampling frequencies
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* Standard interfaces
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** I2C, UART, SDIO, SPI
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* Configurable bidirectional GPIO lanes

Latest revision as of 14:36, 11 March 2018

Edit Values
Myriad 1 MA1110
General Info
DesignerMovidius
ManufacturerTSMC
Model NumberMA1110
MarketEmbedded, Mobile
IntroductionJanuary 15, 2009 (announced)
June, 2009 (launched)
General Specs
FamilyMyriad
Series1
Frequency180 MHz
Microarchitecture
ISASPARC V8 (SPARC), SHAVE (SHAVE)
MicroarchitectureLEON3, SHAVE v2.0
Process65 nm
TechnologyTSMC
Word Size32 bit
Cores9
Threads9
Electrical
Vcore1.2 V
VI/O2.5 V

Myriad 1 MA1110 was a vision processing accelerator designed by Movidius and introduced in 2009.

Overview[edit]

The MA1110 is a vision accelerator designed to work alongside a main host processors, typically in a mobile or embedded device. The MA1110 consists of a single SPARC V8 LEON3 core which is used for management and control and eight SHAVE v2.0 core which are the workhorse of this chip. Each core has 128 KiB of cache. The eight SHAVE cores together are capable of 20GFLOPS of processing power at just a few 100s milliwatt of power.

movidius ma1000 silicon platform.png

Extensions[edit]

  • Host Memory Bus (master and slave): 8-bit / 16-bit / 32-bit
  • Video Output Formats:
    • 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
    • 24bpp, 16M colors, resolutions up to 2048x2048
    • Video support for 4 layers of video and graphics
  • External TV Support
    • Video Output to External HDMI Driver Chip
  • Multiple I2S (Master/Slave) stereo audio channels
    • Independent sampling frequencies
  • Standard interfaces
    • I2C, UART, SDIO, SPI
  • Configurable bidirectional GPIO lanes
Retrieved from "https://en.wikichip.org/w/index.php?title=movidius/myriad/ma1110&oldid=75126"
Facts about "Myriad 1 MA1110 - Intel Movidius"
RDF feed
base frequency180 MHz (0.18 GHz, 180,000 kHz) +
core count9 +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerMovidius +
familyMyriad +
first announcedJanuary 15, 2009 +
first launchedJune 2009 +
full page namemovidius/myriad/ma1110 +
instance ofmicroprocessor +
io voltage2.5 V (25 dV, 250 cV, 2,500 mV) +
isaSPARC V8 + and SHAVE +
isa familySPARC + and SHAVE +
ldateJune 2009 +
manufacturerTSMC +
market segmentEmbedded + and Mobile +
microarchitectureLEON3 + and SHAVE v2.0 +
model numberMA1110 +
nameMyriad 1 MA1110 +
process65 nm (0.065 μm, 6.5e-5 mm) +
series1 +
thread count9 +
word size32 bit (4 octets, 8 nibbles) +