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== Overview ==
 
== Overview ==
 
Introduced in 2008 by [[Freescale]] as a successor to the {{freescale|PowerQUICC}} family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the [[POWER]] architecture. In 2012 Freescale announced the Layerscape series that adopts the [[ARM]] architecture which Freescale/NXP has been using since.
 
Introduced in 2008 by [[Freescale]] as a successor to the {{freescale|PowerQUICC}} family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the [[POWER]] architecture. In 2012 Freescale announced the Layerscape series that adopts the [[ARM]] architecture which Freescale/NXP has been using since.
 +
 +
== Power ==
 +
{{expand section}}
  
 
=== Identification ===
 
=== Identification ===
−
[[File:QorIQ platform levels.png|right|600px]]
 
 
Only applies to original QorIQ P & T series:
 
Only applies to original QorIQ P & T series:
 
{{chip identification
 
{{chip identification
Line 68: Line 70:
 
| desc 6    = '''Iteration/Version'''
 
| desc 6    = '''Iteration/Version'''
 
}}
 
}}
−
 
−
== Series ==
 
−
{{expand section}}
 
  
 
=== P Series ===
 
=== P Series ===
 +
[[File:QorIQ platform levels.png|right|350px]]
 
Announced in mid-2008, the QorIQ P-series are [[POWER]]-based microprocessors based on the {{freescale|e500|l=arch}} microarchitecture. Being the first Freescale multicore networking applications based on the [[45 nm process]], those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.
 
Announced in mid-2008, the QorIQ P-series are [[POWER]]-based microprocessors based on the {{freescale|e500|l=arch}} microarchitecture. Being the first Freescale multicore networking applications based on the [[45 nm process]], those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.
  
 
==== P1 ====
 
==== P1 ====
−
The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.
+
The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. All models exhibit a peak power consumption of sub 5 W. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.
  
 
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{{comp table header|main|5:List of QorIQ P1 Processors}}
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{{comp table header|main|7:List of QorIQ P1 Processors}}
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{{comp table header|cols|Launched|Cores|%Frequency|L2$}}
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{{comp table header|cols|Announced|Cores|Core|%Frequency|L2$|Max Power|Package}}
 
{{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]
 
{{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
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  |?core count
 
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  |?l2$ size#KiB
 
  |?l2$ size#KiB
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{{comp table count|ask=[[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]}}
 
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==== P2 ====
 
==== P2 ====
 
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
 
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
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{{comp table start}}
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<table class="comptable sortable tc4">
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{{comp table header|main|6:List of QorIQ P2 Processors}}
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{{comp table header|cols|Launched|Cores|Core|%Frequency|L2$|Max Power}}
 +
{{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]
 +
|?full page name
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|?model number
 +
|?first launched
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|?core count
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|?core name
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|?base frequency#MHz
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|?l2$ size#KiB
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|?power dissipation#W
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{{comp table count|ask=[[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]}}
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</table>
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== ARM ==
 +
{{empty section}}
  
 
== See also ==
 
== See also ==
 
* [[Cavium]] {{cavium|ThunderX}}
 
* [[Cavium]] {{cavium|ThunderX}}
 
* [[Intel]] {{intel|Atom}}
 
* [[Intel]] {{intel|Atom}}

Latest revision as of 19:23, 31 October 2017

QorIQ
Developer Freescale, NXP
Manufacturer IBM, TSMC
Type System on Chips
Introduction June 16, 2008 (announced)
June 16, 2008 (launch)
Architecture POWER & ARM Communication SoC
Word size 32 bit
4 octets
8 nibbles
, 64 bit
8 octets
16 nibbles
Process 45 nm
0.045 μm
4.5e-5 mm
, 32 nm
0.032 μm
3.2e-5 mm
, 20 nm
0.02 μm
2.0e-5 mm
, 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS
Clock 533 MHz-2,000 MHz
Succession
←
PowerQUICC

QorIQ (pronounced "Core IQ") is a family of ARM and POWER embedded and networking microprocessors designed and sold by NXP (formerly Freescale) since 2008 as a successor to the PowerQUICC family.

Overview[edit]

Introduced in 2008 by Freescale as a successor to the PowerQUICC family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the POWER architecture. In 2012 Freescale announced the Layerscape series that adopts the ARM architecture which Freescale/NXP has been using since.

Power[edit]

New text document.svg This section requires expansion; you can help adding the missing info.

Identification[edit]

Only applies to original QorIQ P & T series:

Identification
QorIQ  P4080 
QorIQ  P1013 
      Iteration/Version
     Core Count
01single-core
02dual-core
04quad-core
08octa-core
    Platform Level
   Technology Node
P45 nm process
T28 nm process
  
 Brand Name
QorIQ

P Series[edit]

QorIQ platform levels.png

Announced in mid-2008, the QorIQ P-series are POWER-based microprocessors based on the e500 microarchitecture. Being the first Freescale multicore networking applications based on the 45 nm process, those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.

P1[edit]

The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. All models exhibit a peak power consumption of sub 5 W. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.

 List of QorIQ P1 Processors
ModelAnnouncedCoresCoreFrequencyL2$Max PowerPackage
P101016 June 20081e500 v2667 MHz
0.667 GHz
667,000 kHz
, 800 MHz
0.8 GHz
800,000 kHz
1.6 W
1,600 mW
0.00215 hp
0.0016 kW
TE-PBGA-II-689, TE-PBGA-425
P101116 June 20081e500 v2800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.56 W
1,560 mW
0.00209 hp
0.00156 kW
TE-PBGA-II-689
P10127 December 20091e500 v2533 MHz
0.533 GHz
533,000 kHz
, 800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.6 W
1,600 mW
0.00215 hp
0.0016 kW
TE-PBGA-II-689
P10139 September 20091e500 v21,067 MHz
1.067 GHz
1,067,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
3 W
3,000 mW
0.00402 hp
0.003 kW
TE-PBGA-II-689
P101420101e500 v2800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.13 W
1,130 mW
0.00152 hp
0.00113 kW
TE-PBGA-II-689, TE-PBGA-425
P1015October 20111e500 v2400 MHz
0.4 GHz
400,000 kHz
, 533 MHz
0.533 GHz
533,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.4 W
1,400 mW
0.00188 hp
0.0014 kW
TE-PBGA-561
P10161e500 v21.53 W
1,530 mW
0.00205 hp
0.00153 kW
TE-PBGA-561
P10171e500 v22 W
2,000 mW
0.00268 hp
0.002 kW
TE-PBGA-457
P102016 June 20082e500 v2800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.89 W
1,890 mW
0.00253 hp
0.00189 kW
TE-PBGA-II-689
P10217 December 20092e500 v21,200 MHz
1.2 GHz
1,200,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
TE-PBGA-II-689
P10229 September 20092e500 v21,067 MHz
1.067 GHz
1,067,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
2.5 W
2,500 mW
0.00335 hp
0.0025 kW
TE-PBGA-II-689
P10232e500 v22 W
2,000 mW
0.00268 hp
0.002 kW
TE-PBGA-457
P1024October 20112e500 v2533 MHz
0.533 GHz
533,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1.6 W
1,600 mW
0.00215 hp
0.0016 kW
TE-PBGA-561
P10252e500 v21.69 W
1,690 mW
0.00227 hp
0.00169 kW
TE-PBGA-561
Count: 14

P2[edit]

The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.

 List of QorIQ P2 Processors
ModelLaunchedCoresCoreFrequencyL2$Max Power
P201020091e500 v21,200 MHz
1.2 GHz
1,200,000 kHz
800 MHz
0.8 GHz
800,000 kHz
1,000 MHz
1 GHz
1,000,000 kHz
1,333 MHz
1.333 GHz
1,333,000 kHz
512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
6.7 W
6,700 mW
0.00898 hp
0.0067 kW
P202020092e500 v2800 MHz
0.8 GHz
800,000 kHz
1,200 MHz
1.2 GHz
1,200,000 kHz
1,333 MHz
1.333 GHz
1,333,000 kHz
512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
8 W
8,000 mW
0.0107 hp
0.008 kW
Count: 2

ARM[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=nxp/qoriq&oldid=66488"
Facts about "QorIQ - NXP"
RDF feed
designerFreescale + and NXP +
first announcedJune 16, 2008 +
first launchedJune 16, 2008 +
full page namenxp/qoriq +
instance ofsystem on a chip family +
main designerFreescale +
manufacturerTSMC + and IBM +
nameQorIQ +
process45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) +