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QorIQ P1012
General Info
Designer	Freescale
Manufacturer	IBM
Model Number	P1012
Market	Networking, Embedded
Introduction	December 7, 2009 (announced) January, 2010 (launched)
General Specs
Family	QorIQ
Series	P1
Frequency	533, 800
Microarchitecture
ISA	Power ISA v2.03 (Power)
Microarchitecture	e500
Core Name	e500 v2
Process	45 nm
Technology	CMOS
Word Size	32 bit
Cores	1
Threads	1
Electrical
Power dissipation	1.6 W
Packaging
Package TE-PBGA-II-689 (TE PBGA-II) Temperature-Enhanced Plastic BGA Dimension 31 mm x 31 mm Contacts 689

QorIQ P1012 is a 32-bit embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 533 MHz (with higher frequencies offered later on) and supports 32-bit DDR3-800 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 8-way set associative Write-through

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Controllers 1 Channels 1 Width 32 bit Max Bandwidth 2.98 GiB/s 3,051.52 MiB/s 3.2 GB/s 3,199.751 MB/s 0.00291 TiB/s 0.0032 TB/s Bandwidth Single 2.98 GiB/s

Expansions

• 3x 10/100/1000 Eithernet with 2x SGMII
• 2x PCIe 1.0a controllers with 4 SerDes
• 2x USB 2.0
• SD/MMC
• SPI
• 2x I2C
• UART
• SEC 3.3 Security Acceleration

Block Diagram

Documents

• P1012/P1021 Product Brief