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Difference between revisions of "intel/xeon w/w-2104"
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{{intel title|Xeon W-2104}}
 
{{intel title|Xeon W-2104}}
−
{{mpu
+
{{chip
 
|future=Yes
 
|future=Yes
 
|name=Xeon W-2104
 
|name=Xeon W-2104
Line 9: Line 9:
 
|part number=CD8067303532903
 
|part number=CD8067303532903
 
|s-spec=SR3LH
 
|s-spec=SR3LH
 +
|s-spec qs=QMW1
 
|market=Workstation
 
|market=Workstation
 
|first announced=August 29, 2017
 
|first announced=August 29, 2017
Line 24: Line 25:
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake (server)
 
|microarch=Skylake (server)
−
|platform=Purley
+
|platform=Basin Falls
 
|core name=Skylake W
 
|core name=Skylake W
 
|core family=6
 
|core family=6
Line 36: Line 37:
 
|max memory=512 GiB
 
|max memory=512 GiB
 
|tdp=120 W
 
|tdp=120 W
−
|package module 1={{packages/intel/fclga-2066}}
+
|tcase min=0 °C
 +
|tcase max=66 °C
 +
|package name 1=intel,fclga_2066
 +
}}
 +
'''W-2104''' is a {{arch|64}} [[quad-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.2 GHz with a [[TDP]] of 120 W and no {{intel|turbo boost}}. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
Note that while this is a [[quad-core]] part, the [[L3 cache]] size is that of a [[hexa-core]] part.
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=4 MiB
 +
|l2 break=4x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=8.25 MiB
 +
|l3 break=6x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=512 GiB
 +
|controllers=2
 +
|channels=4
 +
|max bandwidth=71.53 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|pae=46 bit
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=1
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=No
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}
−
'''W-2123''' is a {{arch|64}} [[quad-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.6 GHz with a [[TDP]] of 120 W and a {{intel|turbo boost}} frequency of up to 3.9 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory.
 

Latest revision as of 09:34, 24 October 2018

Edit Values
Xeon W-2104
intel skylake w (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberW-2104
Part NumberCD8067303532903
S-SpecSR3LH
QMW1 (QS)
MarketWorkstation
IntroductionAugust 29, 2017 (announced)
August 29, 2017 (launched)
Release Price$255.00
ShopAmazon
General Specs
FamilyXeon W
SeriesW-2000
LockedYes
Frequency3,200 MHz
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier32
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformBasin Falls
Core NameSkylake W
Core Family6
Core SteppingU0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP120 W
Tcase0 °C – 66 °C
Packaging
PackageFCLGA-2066 (LGA)
Dimension52.5 mm × 45 mm
Pitch1.016 mm
Contacts2066
SocketSocket R4

W-2104 is a 64-bit quad-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.2 GHz with a TDP of 120 W and no turbo boost. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory.

Cache[edit]

Main article: Skylake § Cache

Note that while this is a quad-core part, the L3 cache size is that of a hexa-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x1 MiB16-way set associativewrite-back
L3$8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
  6x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels4
Max Bandwidth71.53 GiB/s
73,246.72 MiB/s
76.805 GB/s
76,804.753 MB/s
0.0699 TiB/s
0.0768 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Physical Address (PAE)46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (1 Unit)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_w/w-2104&oldid=83674"
Facts about "Xeon W-2104 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon W-2104 - Intel#pcie +
base frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier32 +
core count4 +
core family6 +
core nameSkylake W +
core steppingU0 +
designerIntel +
familyXeon W +
first announcedAugust 29, 2017 +
first launchedAugust 29, 2017 +
full page nameintel/xeon w/w-2104 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description11-way set associative +
l3$ size8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
ldate3000 +
main imageFile:intel skylake w (front).png +
manufacturerIntel +
market segmentWorkstation +
max case temperature339.15 K (66 °C, 150.8 °F, 610.47 °R) +
max cpu count1 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels4 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberW-2104 +
nameXeon W-2104 +
number of avx-512 execution units1 +
packageFCLGA-2066 +
part numberCD8067303532903 +
platformBasin Falls +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 255.00 (€ 229.50, £ 206.55, ¥ 26,349.15) +
s-specSR3LH +
s-spec (qs)QMW1 +
seriesW-2000 +
smp max ways1 +
socketSocket R4 +
supported memory typeDDR4-2400 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +