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Difference between revisions of "intel/xeon gold/6134"
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{{intel title|Xeon Gold 6134}} | {{intel title|Xeon Gold 6134}} | ||
− | {{ | + | {{chip |
|name=Xeon Gold 6134 | |name=Xeon Gold 6134 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 15: | Line 15: | ||
|release price=$2214.00 | |release price=$2214.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6100 |
|locked=Yes | |locked=Yes | ||
|frequency=3,200 MHz | |frequency=3,200 MHz | ||
Line 26: | Line 26: | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 37: | Line 37: | ||
|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=130 W | |tdp=130 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=79 °C | |tcase max=79 °C | ||
− | |package | + | |dts min=0 °C |
+ | |dts max=100 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |successor=Xeon Gold 6234 | ||
+ | |successor link=intel/xeon_gold/6234 | ||
}} | }} | ||
− | '''Xeon Gold 6134''' is a {{arch|64}} [[octa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6134, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 130 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | + | '''Xeon Gold 6134''' is a {{arch|64}} [[octa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6134, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 130 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
The Xeon Gold 6134 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | The Xeon Gold 6134 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | ||
{{cache size | {{cache size | ||
Line 214: | Line 221: | ||
|freq_avx512_7=2,700 MHz | |freq_avx512_7=2,700 MHz | ||
|freq_avx512_8=2,700 MHz | |freq_avx512_8=2,700 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00322.html|test_timestamp=2017-10-29 15:10:57-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)|SPECrate2017_int_base=106|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00325.html|test_timestamp=2017-10-30 01:48:09-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)|SPECrate2017_fp_base=123|SPECrate2017_fp_peak=}} | ||
}} | }} | ||
[[Category:microprocessor models by intel based on skylake extreme core count die]] | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6134 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6134 |
Part Number | BX806736134, CD8067303330302 |
S-Spec | SR3AR QMRL (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2214.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 3,200 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 130 W |
Tcase | 0 °C – 79 °C |
TDTS | 0 °C – 100 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6134 is a 64-bit octa-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6134, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 130 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6134 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 3,200 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz |
AVX2 | 2,700 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-29 15:10:57-0400
Chips: 2, Cores: 16, Copies: 32
Vendor: HPE
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
Tested: 2017-10-29 15:10:57-0400
Chips: 2, Cores: 16, Copies: 32
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
SPECrate2017_int_base: 106
Test: SPEC CPU2017
Tested: 2017-10-30 01:48:09-0400
Chips: 2, Cores: 16, Copies: 32
Vendor: HPE
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
Tested: 2017-10-30 01:48:09-0400
Chips: 2, Cores: 16, Copies: 32
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
SPECrate2017_fp_base: 123
Facts about "Xeon Gold 6134 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6134 - Intel#io +, Xeon Gold 6134 - Intel + and Xeon Gold 6134 - Intel + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 32 + |
core count | 8 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/6134 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | July 11, 2017 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 352.15 K (79 °C, 174.2 °F, 633.87 °R) + |
max cpu count | 4 + |
max dts temperature | 100 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 6134 + |
name | Xeon Gold 6134 + |
package | FCLGA-3647 + |
part number | BX806736134 + and CD8067303330302 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,214.00 (€ 1,992.60, £ 1,793.34, ¥ 228,772.62) + |
s-spec | SR3AR + |
s-spec (qs) | QMRL + |
series | 6100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 130 W (130,000 mW, 0.174 hp, 0.13 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |