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Difference between revisions of "fujitsu/sparc64/sparc64 xii"
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{{fujitsu title|SPARC64 XII}} | {{fujitsu title|SPARC64 XII}} | ||
| − | {{ | + | {{chip |
| name = SPARC64 XII | | name = SPARC64 XII | ||
| image = sparc64 xii.png | | image = sparc64 xii.png | ||
| Line 9: | Line 9: | ||
| model number = SPARC64 XII | | model number = SPARC64 XII | ||
| part number = | | part number = | ||
| − | | part number | + | | part number 2 = |
| market = Server | | market = Server | ||
| first announced = 2015 | | first announced = 2015 | ||
Latest revision as of 13:39, 24 March 2019
| Edit Values | |
| SPARC64 XII | |
 | |
| SPARC64 XII Chip | |
| General Info | |
| Designer | Fujitsu |
| Manufacturer | TSMC |
| Model Number | SPARC64 XII |
| Market | Server |
| Introduction | 2015 (announced) April 4, 2017 (launched) |
| General Specs | |
| Family | SPARC64 |
| Frequency | 4,250 MHz |
| Microarchitecture | |
| ISA | SPARC V9 (SPARC) |
| Microarchitecture | SPARC64 XII |
| Process | 20 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 12 |
| Threads | 96 |
| Max Memory | 2 TiB |
| Multiprocessing | |
| Max SMP | 32-Way (Multiprocessor) |
SPARC64 XII is a high-performance 64-bit dodeca-core SPARC microprocessor designed by Fujitsu and introduced in April 2017.
Cache[edit]
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Expansions[edit]
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Die Shot[edit]
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Facts about "SPARC64 XII - Fujitsu"
| base frequency | 4,250 MHz (4.25 GHz, 4,250,000 kHz) + |
| core count | 12 + |
| designer | Fujitsu + |
| family | SPARC64 + |
| first announced | 2015 + |
| first launched | April 4, 2017 + |
| full page name | fujitsu/sparc64/sparc64 xii + |
| instance of | microprocessor + |
| isa | SPARC V9 + |
| isa family | SPARC + |
| ldate | April 4, 2017 + |
| main image |  + |
| main image caption | SPARC64 XII Chip + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 32 + |
| max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
| microarchitecture | SPARC64 XII + |
| model number | SPARC64 XII + |
| name | SPARC64 XII + |
| process | 20 nm (0.02 μm, 2.0e-5 mm) + |
| smp max ways | 32 + |
| technology | CMOS + |
| thread count | 96 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
