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:{{hisil|taishan_v110|TaiShan|l=arch}} (uarch)
 
:{{hisil|taishan_v110|TaiShan|l=arch}} (uarch)
  
−
=== Kirin 9000E, 9000L, 9000 5G/4G series ===
+
=== Kirin 900 series ===
−
Kirin 9000 is [[HiSilicon]]'s first SoC based on [[5 nm]]+ FinFET (EUV) [[TSMC]] technology (N5 node)  
+
 
 +
:;Kirin 950, 955
 +
'''Kirin 950''' ([[Hi3650]])/'''Kirin 955''' SoCs based on [[TSMC]] [[16 nm]] FinFET+ technology.
 +
*Supports: SD 4.1 (UHS-II), UFS 2.0, eMMC 5.1, 802.11ac Wi-Fi, Bluetooth 4.2 Smart, USB 3.0
 +
:NFS, Dual ISP (42MP), Native 10-bit 4K video encode, i5 coprocessor, Tensilica HiFi 4 DSP
 +
 
 +
:;Kirin 960
 +
'''Kirin 960''' ([[Hi3660]]) SoC based on [[TSMC]] [[16 nm]] FFC technology.
 +
* Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6
 +
 
 +
:; [[Kirin 970]]
 +
'''[[Kirin 970]]''' ([[Hi3670]]) SoC based on [[TSMC]] [[10 nm]] FinFET+ technology.
 +
* Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
 +
* Cadence Tensilica Vision P6 DSP
 +
* NPU made in collaboration with ''Cambricon Technologies'' (1.92T FP16 OPS)
 +
 
 +
:; [[Kirin 980]]
 +
'''[[Kirin 980]]''' is [[HiSilicon]]'s SoC based on [[7 nm]] FinFET technology.
 +
* Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
 +
* Dual NPU made in collaboration with ''Cambricon Technologies''.
 +
 
 +
:; Kirin 985 4G/5G
 +
'''Kirin 985 4G''' is [[Hisilicon]]'s 4G SoC based on [[7 nm]] FinFET technology. <br>
 +
'''Kirin 985 5G''' is [[Hisilicon]]'s 5G SoC based on [[7 nm]] FinFET technology.
 +
* Interconnect: ARM Mali-G77 MP8, Storage UFS 3.0
 +
* Big-Tiny Da Vinci NPU: 1x Da Vinci Lite + 1x Da Vinci Tiny
 +
 
 +
:; Kirin 990 4G/5G, 990E 5G
 +
'''[[Kirin 990 4G]]''' is [[HiSilicon]]'s 4G SoC based on N[[7 nm]] FinFET technology. <br>
 +
'''[[Kirin 990 5G]]''' is [[HiSilicon]]'s 5G SoC based on N[[7 nm]]+ FinFET technology. <br>
 +
'''Kirin 990E 5G''' is [[HiSilicon]]'s 5G SoC based on N[[7 nm]]+ FinFET technology.
 +
*Interconnect
 +
**[[Kirin 990 4G]]: ARM Mali-G76 MP16
 +
**[[Kirin 990 5G]]: ARM Mali-G76 MP16
 +
**Kirin 990E 5G: ARM Mali-G76 MP14
 +
*Da Vinci NPU
 +
**[[Kirin 990 4G]]: 1x Da Vinci Lite + 1x Da Vinci Tiny
 +
**[[Kirin 990 5G]]: 2x Da Vinci Lite + 1x Da Vinci Tiny
 +
**Kirin 990E 5G: 1x Da Vinci Lite + 1x Da Vinci Tiny
 +
*Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs
 +
:+ 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
 +
*Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs
 +
:+ 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)
 +
 
 +
{| class="wikitable"
 +
|-
 +
! rowspan="2" | Model number
 +
! rowspan="2" | Fab node
 +
! colspan="4" | CPU
 +
! colspan="2" | GPU
 +
! colspan="3" | Memory technology
 +
! rowspan="2" | Sampling <br>availability
 +
|-
 +
! [[ISA]]
 +
! [[Microarchitecture|µarch]]
 +
! Cores
 +
! Freq (GHz)
 +
! [[Microarchitecture|µarch]]
 +
! Freq <br>(MHz)
 +
! Type
 +
! Bus width <br>(bit)
 +
! Band width <br>(GB/s)
 +
|-
 +
| '''Kirin 950''' <br>([[Hi3650]])
 +
| rowspan="2" | [[TSMC]] <br>[[16 nm]] <br>FinFET+
 +
| rowspan="2" | [[ARMv8]]-A
 +
| rowspan="2" | [[Cortex-A72]] <br>[[Cortex-A53]] <br>({{armh|big.LITTLE}})
 +
| rowspan="2" | 4+4
 +
| 2.3&nbsp;(A72)<br>1.8&nbsp;(A53)
 +
| rowspan="2" | Mali-T880 <br>MP4
 +
| rowspan="2" | 900&nbsp;MHz <br>(168 <br>GFLOPS <br>in FP32)
 +
| LPDDR4 || rowspan="2" | 64-bit (2x 32-bit) <br>Dual-channel || rowspan="2" | (25.6 MB/s)
 +
| Q4 2015
 +
|-
 +
| '''Kirin 955'''
 +
| 2.5&nbsp;(A72)<br>1.8&nbsp;(A53)
 +
| LPDDR3 <br>(3&nbsp;GB) <br>LPDDR4 <br>(4&nbsp;GB)
 +
| Q2 2016
 +
|-
 +
| '''Kirin 960''' <br>([[Hi3660]])
 +
| [[TSMC]] <br>[[16 nm]] <br>FFC
 +
| [[ARMv8]]-A
 +
| {{armh|Cortex-A73|l=arch}} <br>[[Cortex-A53]] <br>({{armh|big.LITTLE}})
 +
| 4+4
 +
| 2.36&nbsp;(A73)<br>1.84&nbsp;(A53)
 +
| Mali-G71 <br>MP8
 +
| 1037&nbsp;MHz<br>(199.1 <br>GFLOPS <br>in FP32)
 +
| LPDDR4<br>-1600 || 64-bit (2x 32-bit) <br>Dual-channel || (28.8 MB/s)
 +
| Q4 2016
 +
|-
 +
| '''[[Kirin 970]]''' <br>([[Hi3670]])
 +
| [[TSMC]] <br>[[10 nm]] <br>FinFET+
 +
| [[ARMv8]]-A
 +
| {{armh|Cortex-A73|l=arch}} <br>[[Cortex-A53]] <br>({{armh|big.LITTLE}})
 +
| 4+4
 +
| 2.36&nbsp;(A73)<br>1.84&nbsp;(A53)
 +
| Mali-G72 <br>MP12
 +
| 746&nbsp;MHz<br>(214.8 <br>GFLOPS <br>in FP32)
 +
| LPDDR4X<br>-1866 || 64-bit (4x16-bit) <br>Quad-channel || (29.8 MB/s)
 +
| Q4 2017
 +
|-
 +
| '''[[Kirin 980]]'''
 +
| rowspan="2" | [[TSMC]] <br>[[7 nm]] <br>FinFET
 +
| rowspan="2" | [[ARMv8|ARM<br>v8.2-A]]
 +
| rowspan="2" | [[Cortex-A76]] <br>[[Cortex-A55]] <br>({{armh|big.LITTLE}})
 +
| (2+2)+4
 +
| 2.6&nbsp;(A76&nbsp;H)<br>1.92&nbsp;(A76&nbsp;L)<br>1.8&nbsp;(A55)
 +
| Mali-G76 <br>MP10
 +
| 720&nbsp;MHz<br>(345.6 <br>GFLOPS <br>in FP32)
 +
| rowspan="2" | LPDDR4X<br>-2133
 +
| rowspan="2" | 64-bit (4x16-bit) <br>Quad-channel
 +
| rowspan="2" | LPDDR4X<br>(34.1 MB/s)
 +
| Q4 2018
 +
|-
 +
| '''Kirin 985 4G'''<br>'''Kirin 985 5G''' <br>(Hi6290V110)
 +
| (1+3)+4
 +
| 2.58&nbsp;(A76&nbsp;H)<br>2.40&nbsp;(A76&nbsp;L)<br>1.84&nbsp;(A55)
 +
| Mali-G77 <br>MP8
 +
| 700&nbsp;MHz<br>(358.4 <br>GFLOPS <br>in FP32)
 +
| Q2 2020
 +
|-
 +
| '''[[Kirin 990 4G]]'''
 +
| [[TSMC]] <br>[[7 nm]] <br>FinFET <br>(DUV)
 +
| rowspan="3" | [[ARMv8|ARM<br>v8.2-A]]
 +
| rowspan="3" | [[Cortex-A76]] <br>[[Cortex-A55]] <br>({{armh|big.LITTLE}})
 +
| rowspan="3" | (2+2)+4
 +
| 2.86&nbsp;(A76&nbsp;H)<br>2.09&nbsp;(A76&nbsp;L)<br>1.86&nbsp;(A55)
 +
| rowspan="2" | Mali-G76 <br>MP16
 +
| rowspan="2" | 600&nbsp;MHz<br>(460.8 <br>GFLOPS <br>in FP32)
 +
| rowspan="3" | LPDDR4X<br>-2133 || rowspan="3" | 64-bit (4x16-bit) <br>Quad-channel
 +
| rowspan="3" | LPDDR4X<br>(34.1 GB/s)
 +
| rowspan="2" | Q4 2019
 +
|-
 +
| '''[[Kirin 990 5G]]'''
 +
| rowspan="2" | [[TSMC]] <br>[[7 nm]]+ <br>FinFET <br>(EUV)
 +
| rowspan="2" | 2.86&nbsp;(A76&nbsp;H)<br>2.36&nbsp;(A76&nbsp;L)<br>1.95&nbsp;(A55)
 +
|-
 +
| '''Kirin 990E 5G'''
 +
| Mali-G76 <br>MP14
 +
| 600&nbsp;MHz<br>(403.2 <br>GFLOPS <br>in FP32)
 +
| Q4 2020
 +
|-
 +
|}
 +
 
 +
=== Kirin 9000 series ===
 +
:; Kirin 9000E, 9000L, 9000 5G/4G
 +
'''Kirin 9000''' is [[HiSilicon]]'s first SoC based on [[5 nm]]+ FinFET (EUV) [[TSMC]] technology (N5 node)  
 
:and the first [[5 nm]] SoC to be launched on the international market. <ref>{{cite book |title=Kirin 9000 |website=hisilicon.com |url=https://www.hisilicon.com/en/products/Kirin/Kirin-flagship-chips/Kirin-9000 |date=16 September 2021}}</ref>  
 
:and the first [[5 nm]] SoC to be launched on the international market. <ref>{{cite book |title=Kirin 9000 |website=hisilicon.com |url=https://www.hisilicon.com/en/products/Kirin/Kirin-flagship-chips/Kirin-9000 |date=16 September 2021}}</ref>  
  
Line 30: Line 176:
 
*[[24-core]] Mali-G78 GPU (22-core in the Kirin 9000E version)  
 
*[[24-core]] Mali-G78 GPU (22-core in the Kirin 9000E version)  
  
−
The Kirin 9000L uses a 1+2+3 core configuration:  
+
'''Kirin 9000L''' uses a 1+2+3 core configuration:  
 
*3x ARM Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz),  
 
*3x ARM Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz),  
 
*3x ARM Cortex-A55 (3x 2.05 GHz) and  
 
*3x ARM Cortex-A55 (3x 2.05 GHz) and  
Line 42: Line 188:
 
:Due to the integrated 3rd generation 5G proprietary modem "Balong 5000", Kirin 9000 supports 2G, 3G, 4G and 5G SA & NSA Sub-6 GHz connectivity. The SoC's Thermal design power (TDP) is 6 W.
 
:Due to the integrated 3rd generation 5G proprietary modem "Balong 5000", Kirin 9000 supports 2G, 3G, 4G and 5G SA & NSA Sub-6 GHz connectivity. The SoC's Thermal design power (TDP) is 6 W.
 
The 2021 4G version of the Kirin 9000 has the Balong modem limited via software to comply with the ban  
 
The 2021 4G version of the Kirin 9000 has the Balong modem limited via software to comply with the ban  
−
:imposed on Huawei by the US government for non-chinese 5G technologies.  
+
:imposed on Huawei by the US government for non-chinese 5G technologies. -->
−
The Kirin 9006C is a rebranded variant of the Kirin 9000E for the Huawei Qingyun L420 and L540 laptops. -->
+
'''Kirin 9006C''' is a rebranded variant of the '''Kirin 9000E'''
 +
:for the '''Huawei''' ''Qingyun'' L420 and L540 laptops.  
 
:;Spec
 
:;Spec
 
* GPU
 
* GPU
Line 125: Line 272:
 
|-
 
|-
 
| '''Kirin 9000S''' <br>(Hi36A0V120)
 
| '''Kirin 9000S''' <br>(Hi36A0V120)
−
| rowspan="17" | [[SMIC]] <br>''N+2'' <br>[[7 nm]] <br>[[FinFET]]
+
| rowspan="9" | [[SMIC]] <br>''N+2'' <br>[[7 nm]] <br>[[FinFET]]
−
| rowspan="17" | [[ARMv8]].x
+
| rowspan="9" | [[ARMv8]].x
−
| rowspan="15" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}, <br>[[Cortex-A510]]
+
| rowspan="9" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}, <br>[[Cortex-A510]]
−
| rowspan="7"| 1+3+4 (8)<hr>2+6+4 (12)
+
| rowspan="7" | 1+3+4 (8)<hr>2+6+4 (12)
 
| 2.62 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| 2.62 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
−
| rowspan="15" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>910
+
| rowspan="9" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>910
−
| rowspan="15" | 750 <br>MHz
+
| rowspan="9" | 750 <br>MHz
−
| rowspan="17" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
+
| rowspan="9" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
−
| rowspan="17" | 64-bit <br>(4x16-bit) <br>Quad-<br>channel
+
| rowspan="9" | 64-bit <br>(4x16-bit) <br>Quad-<br>channel
−
| rowspan="17" | LPDDR5<br>(51.2 MB/s)<br>LPDDR5X<br>(68.2 MB/s)
+
| rowspan="9" | LPDDR5<br>(51.2 MB/s)<br>LPDDR5X<br>(68.2 MB/s)
 
| Q3 2023
 
| Q3 2023
 
|-
 
|-
 
| '''Kirin 9000S1''' <br>(Hi36A0V120)
 
| '''Kirin 9000S1''' <br>(Hi36A0V120)
−
| rowspan="6"| 2.49 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
+
| rowspan="6" | 2.49 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| Q1 2024
 
| Q1 2024
 
|-
 
|-
Line 157: Line 304:
 
|-
 
|-
 
| '''Kirin 9000SL''' <br>(Hi36A0V120)
 
| '''Kirin 9000SL''' <br>(Hi36A0V120)
−
| rowspan="2"| 1+2+3 (6)<hr>2+4+3 (9)
+
| rowspan="2" | 1+2+3 (6)<hr>2+4+3 (9)
−
| rowspan="2"| 2.35 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
+
| rowspan="2" | 2.35 GHz <br>(TaishanV120)<br>2.15 GHz <br>(TaishanV120)<br>1.53 GHz <br>([[Cortex-A510]])
 
| Q4 2023
 
| Q4 2023
 
|-
 
|-
Line 165: Line 312:
 
|-
 
|-
 
| '''Kirin 9010''' <br>(Hi36A0V121)
 
| '''Kirin 9010''' <br>(Hi36A0V121)
−
| rowspan="5"| 1+3+4 (8) <hr>2+6+4 (12)
+
| rowspan="6" | [[SMIC]] <br>''N+2'' <br>[[7 nm]] <br>[[FinFET]]
 +
| rowspan="6" | [[ARMv8]].x
 +
| rowspan="6" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}, <br>[[Cortex-A510]]
 +
| rowspan="5" | 1+3+4 (8) <hr>2+6+4 (12)
 
| 2.30 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| 2.30 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 +
| rowspan="6" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>910
 +
| rowspan="6" | 750 <br>MHz
 +
| rowspan="6" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
 +
| rowspan="6" | 64-bit <br>(4x16-bit) <br>Quad-<br>channel
 +
| rowspan="6" | LPDDR5<br>(51.2 MB/s)<br>LPDDR5X<br>(68.2 MB/s)
 
| Q2 2024
 
| Q2 2024
 
|-
 
|-
 
| '''Kirin 9010E''' <br>(Hi36A0V121)
 
| '''Kirin 9010E''' <br>(Hi36A0V121)
−
| rowspan="4"| 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
+
| rowspan="4" | 2.19 GHz <br>(TaishanV121)<br>2.18 GHz <br>(TaishanV120)<br>1.55 GHz <br>([[Cortex-A510]])
 
| Q3 2024
 
| Q3 2024
 
|-
 
|-
Line 188: Line 343:
 
|-
 
|-
 
| '''Kirin 9020''' <br>(Hi36C0V110)
 
| '''Kirin 9020''' <br>(Hi36C0V110)
 +
| rowspan="2" | [[SMIC]] <br>''N+2'' <br>[[7 nm]] <br>[[FinFET]]
 +
| rowspan="2" | [[ARMv8]].x
 
| rowspan="2" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}
 
| rowspan="2" | [[HiSilicon]] <br>{{hisil|taishan_v110|TaiShan|l=arch}}
 
| rowspan="2" | 1+3+4 (8) <hr>2+6+4 (12)
 
| rowspan="2" | 1+3+4 (8) <hr>2+6+4 (12)
Line 193: Line 350:
 
| rowspan="2" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>920
 
| rowspan="2" | [[HiSilicon]] <br>{{hisil|maleoon|Maleoon|l=arch}} <br>920
 
| rowspan="2" | 840 <br>MHz
 
| rowspan="2" | 840 <br>MHz
 +
| rowspan="2" | LPDDR5<br>-6400 <br>LPDDR5X<br>-8533
 +
| rowspan="2" | 64-bit <br>(4x16-bit) <br>Quad-<br>channel
 +
| rowspan="2" | LPDDR5<br>(51.2 MB/s)<br>LPDDR5X<br>(68.2 MB/s)
 
| Q4 2024
 
| Q4 2024
 
|-
 
|-

Latest revision as of 19:57, 28 March 2025


HiSilicon[edit]

Family[edit]

Kirin
TaiShan (uarch)

Kirin 900 series[edit]

Kirin 950, 955

Kirin 950 (Hi3650)/Kirin 955 SoCs based on TSMC 16 nm FinFET+ technology.

  • Supports: SD 4.1 (UHS-II), UFS 2.0, eMMC 5.1, 802.11ac Wi-Fi, Bluetooth 4.2 Smart, USB 3.0
NFS, Dual ISP (42MP), Native 10-bit 4K video encode, i5 coprocessor, Tensilica HiFi 4 DSP
Kirin 960

Kirin 960 (Hi3660) SoC based on TSMC 16 nm FFC technology.

  • Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6
Kirin 970

Kirin 970 (Hi3670) SoC based on TSMC 10 nm FinFET+ technology.

  • Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
  • Cadence Tensilica Vision P6 DSP
  • NPU made in collaboration with Cambricon Technologies (1.92T FP16 OPS)
Kirin 980

Kirin 980 is HiSilicon's SoC based on 7 nm FinFET technology.

  • Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
  • Dual NPU made in collaboration with Cambricon Technologies.
Kirin 985 4G/5G

Kirin 985 4G is Hisilicon's 4G SoC based on 7 nm FinFET technology.
Kirin 985 5G is Hisilicon's 5G SoC based on 7 nm FinFET technology.

  • Interconnect: ARM Mali-G77 MP8, Storage UFS 3.0
  • Big-Tiny Da Vinci NPU: 1x Da Vinci Lite + 1x Da Vinci Tiny
Kirin 990 4G/5G, 990E 5G

Kirin 990 4G is HiSilicon's 4G SoC based on N7 nm FinFET technology.
Kirin 990 5G is HiSilicon's 5G SoC based on N7 nm+ FinFET technology.
Kirin 990E 5G is HiSilicon's 5G SoC based on N7 nm+ FinFET technology.

  • Interconnect
  • Da Vinci NPU
    • Kirin 990 4G: 1x Da Vinci Lite + 1x Da Vinci Tiny
    • Kirin 990 5G: 2x Da Vinci Lite + 1x Da Vinci Tiny
    • Kirin 990E 5G: 1x Da Vinci Lite + 1x Da Vinci Tiny
  • Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs
+ 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
  • Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs
+ 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)
Model number Fab node CPU GPU Memory technology Sampling
availability
ISA µarch Cores Freq (GHz) µarch Freq
(MHz) 		Type Bus width
(bit) 		Band width
(GB/s)
Kirin 950
(Hi3650) 		TSMC
16 nm
FinFET+ 		ARMv8-A Cortex-A72
Cortex-A53
(big.LITTLE) 		4+4 2.3 (A72)
1.8 (A53) 		Mali-T880
MP4 		900 MHz
(168
GFLOPS
in FP32) 		LPDDR4 64-bit (2x 32-bit)
Dual-channel 		(25.6 MB/s) Q4 2015
Kirin 955 2.5 (A72)
1.8 (A53) 		LPDDR3
(3 GB)
LPDDR4
(4 GB) 		Q2 2016
Kirin 960
(Hi3660) 		TSMC
16 nm
FFC 		ARMv8-A Cortex-A73
Cortex-A53
(big.LITTLE) 		4+4 2.36 (A73)
1.84 (A53) 		Mali-G71
MP8 		1037 MHz
(199.1
GFLOPS
in FP32) 		LPDDR4
-1600 		64-bit (2x 32-bit)
Dual-channel 		(28.8 MB/s) Q4 2016
Kirin 970
(Hi3670) 		TSMC
10 nm
FinFET+ 		ARMv8-A Cortex-A73
Cortex-A53
(big.LITTLE) 		4+4 2.36 (A73)
1.84 (A53) 		Mali-G72
MP12 		746 MHz
(214.8
GFLOPS
in FP32) 		LPDDR4X
-1866 		64-bit (4x16-bit)
Quad-channel 		(29.8 MB/s) Q4 2017
Kirin 980 TSMC
7 nm
FinFET 		ARM
v8.2-A 		Cortex-A76
Cortex-A55
(big.LITTLE) 		(2+2)+4 2.6 (A76 H)
1.92 (A76 L)
1.8 (A55) 		Mali-G76
MP10 		720 MHz
(345.6
GFLOPS
in FP32) 		LPDDR4X
-2133 		64-bit (4x16-bit)
Quad-channel 		LPDDR4X
(34.1 MB/s) 		Q4 2018
Kirin 985 4G
Kirin 985 5G
(Hi6290V110) 		(1+3)+4 2.58 (A76 H)
2.40 (A76 L)
1.84 (A55) 		Mali-G77
MP8 		700 MHz
(358.4
GFLOPS
in FP32) 		Q2 2020
Kirin 990 4G TSMC
7 nm
FinFET
(DUV) 		ARM
v8.2-A 		Cortex-A76
Cortex-A55
(big.LITTLE) 		(2+2)+4 2.86 (A76 H)
2.09 (A76 L)
1.86 (A55) 		Mali-G76
MP16 		600 MHz
(460.8
GFLOPS
in FP32) 		LPDDR4X
-2133 		64-bit (4x16-bit)
Quad-channel 		LPDDR4X
(34.1 GB/s) 		Q4 2019
Kirin 990 5G TSMC
7 nm+
FinFET
(EUV) 		2.86 (A76 H)
2.36 (A76 L)
1.95 (A55)
Kirin 990E 5G Mali-G76
MP14 		600 MHz
(403.2
GFLOPS
in FP32) 		Q4 2020

Kirin 9000 series[edit]

Kirin 9000E, 9000L, 9000 5G/4G

Kirin 9000 is HiSilicon's first SoC based on 5 nm+ FinFET (EUV) TSMC technology (N5 node)

and the first 5 nm SoC to be launched on the international market. [1]

This octa-core system on a chip is based on the 9th Gen of the HiSilicon Kirin series

and is equipped with 15.3 billion transistors in a 1+3+4 core configuration:
  • 4x ARM Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz),
  • 4x ARM Cortex-A55 (4x 2.05 GHz) and
  • 24-core Mali-G78 GPU (22-core in the Kirin 9000E version)

Kirin 9000L uses a 1+2+3 core configuration:

  • 3x ARM Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz),
  • 3x ARM Cortex-A55 (3x 2.05 GHz) and
  • 22-core Mali-G78 GPU with Kirin Gaming + 3.0 implementation

Kirin 9006C is a rebranded variant of the Kirin 9000E

for the Huawei Qingyun L420 and L540 laptops.
Spec
  • GPU
    • Kirin 9000L: ARM Mali-G78 MP22
    • Kirin 9000E: ARM Mali-G78 MP22
    • Kirin 9000: ARM Mali-G78 MP24
  • Da Vinci NPU architecture 2.0
    • Kirin 9000L: 1x Big Core + 1x Tiny Core
    • Kirin 9000E: 1x Big Core + 1x Tiny Core
    • Kirin 9000: 2x Big Cores + 1x Tiny Core
Model number Fab node CPU GPU Memory technology Sampling
availability
ISA µarch Cores Freq (GHz) µarch Freq
(MHz) 		Type Bus width
(bit) 		Band width
(GB/s)
Kirin 9000L TSMC 5 nm+
FinFET (EUV) 		ARM
v8.2-A 		Cortex-A77
Cortex-A55
(big.LITTLE) 		(1+2)+3 3.13 (A77 H)
2.54 (A77 L)
2.05 (A55) 		Mali-G78
MP22 		759 MHz
(1068.7
GFLOPS
in FP32) 		LPDDR4X
-2133
LPDDR5
-2750 		64-bit (4x16-bit)
Quad-channel 		LPDDR4X
(34.1 GB/s)
LPDDR5
(44.0 GB/s) 		Q4 2020
Kirin 9000E (1+3)+4
Kirin 9000
(Hi36A0V101)
Kirin 9000 4G
Kirin 9000 5G 		Mali-G78
MP24 		759 MHz
(1165.8
GFLOPS
in FP32)

Kirin 9000S, 9010, 9020 series[edit]

The Kirin 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 (Hi36A0) family are the first HiSilicon-developed SoCs manufactured

in high volumes in mainland China by Semiconductor Manufacturing International Corporation (SMIC).

The SoCs are based on SMIC's 7 nm technology node, referred to as "N+2".

It also includes 1x Da Vinci "big" NPU core and 1x Da Vinci "small" NPU core.
Model number Fab node CPU GPU Memory technology Sampling
availability
ISA µarch Cores (total)
Threads (total) 		Freq (GHz) µarch Freq
(MHz) 		Type Bus width
(bit) 		Band width
(GB/s)
Kirin 9000S
(Hi36A0V120) 		SMIC
N+2
7 nm
FinFET 		ARMv8.x HiSilicon
TaiShan,
Cortex-A510 		1+3+4 (8)
2+6+4 (12) 		2.62 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		HiSilicon
Maleoon
910 		750
MHz 		LPDDR5
-6400
LPDDR5X
-8533 		64-bit
(4x16-bit)
Quad-
channel 		LPDDR5
(51.2 MB/s)
LPDDR5X
(68.2 MB/s) 		Q3 2023
Kirin 9000S1
(Hi36A0V120) 		2.49 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		Q1 2024
Kirin 9000W
(Hi36A0V120) 		Q4 2023
Kirin 9000WL
(Hi36A0V120) 		Q2 2024
Kirin 9000WE
(Hi36A0V120) 		Q2 2024
Kirin T90
(Hi36A0V120) 		Q3 2024
Kirin T90A
(Hi36A0V120) 		Q3 2024
Kirin 9000SL
(Hi36A0V120) 		1+2+3 (6)
2+4+3 (9) 		2.35 GHz
(TaishanV120)
2.15 GHz
(TaishanV120)
1.53 GHz
(Cortex-A510) 		Q4 2023
Kirin 9000WM
(Hi36A0V120) 		Q2 2024
Kirin 9010
(Hi36A0V121) 		SMIC
N+2
7 nm
FinFET 		ARMv8.x HiSilicon
TaiShan,
Cortex-A510 		1+3+4 (8)
2+6+4 (12) 		2.30 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.55 GHz
(Cortex-A510) 		HiSilicon
Maleoon
910 		750
MHz 		LPDDR5
-6400
LPDDR5X
-8533 		64-bit
(4x16-bit)
Quad-
channel 		LPDDR5
(51.2 MB/s)
LPDDR5X
(68.2 MB/s) 		Q2 2024
Kirin 9010E
(Hi36A0V121) 		2.19 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.55 GHz
(Cortex-A510) 		Q3 2024
Kirin 9010A
(Hi36A0V121) 		Q3 2024
Kirin 9010W
(Hi36A0V121) 		Q3 2024
Kirin T91
(Hi36A0V121) 		Q3 2024
Kirin 9010L
(Hi36A0V121) 		1+2+3 (6)
2+4+3 (9) 		2.19 GHz
(TaishanV121)
2.18 GHz
(TaishanV120)
1.40 GHz
(Cortex-A510) 		Q2 2024
Kirin 9020
(Hi36C0V110) 		SMIC
N+2
7 nm
FinFET 		ARMv8.x HiSilicon
TaiShan 		1+3+4 (8)
2+6+4 (12) 		2.50 GHz
(TaishanV123)
2.15 GHz
(TaishanV120)
1.60 GHz
(Taishan-Little) 		HiSilicon
Maleoon
920 		840
MHz 		LPDDR5
-6400
LPDDR5X
-8533 		64-bit
(4x16-bit)
Quad-
channel 		LPDDR5
(51.2 MB/s)
LPDDR5X
(68.2 MB/s) 		Q4 2024
Kirin T92
(Hi36C0V110) 		Q4 2024

Server processors[edit]

HiSilicon develops server processor SoCs based on the ARM architecture.

Hi1610[edit]

The Hi1610 is HiSilicon's first generation server processor announced in 2015.

It features:
  • 16x ARM Cortex-A57 @ 2.1GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 16MB CCN L3
  • TSMC 16 nm process
  • 2x DDR4-1866 memory
  • 16x PCIe 3.0 ports

Hi1612[edit]

The Hi1612 is HiSilicon's second generation server processor launched in 2016.

It is the first chiplet-based Kunpeng with two computing dies. It features:
  • 32x ARM Cortex-A57 @ 2.1GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
  • TSMC 16 nm process
  • 4x DDR4-2133 memory
  • 16x PCIe 3.0 ports

Kunpeng 916 (Hi1616)[edit]

The Kunpeng 916 (Hi1616) is HiSilicon's third generation server processor launched in 2017.

The Kunpeng 916 is used in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server,
TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server. It features:
  • 32x ARM Cortex-A72 @ 2.4GHz cores
  • 48KB L1-I, 32KB L1-D, 1MB L2/4 cores, 32MB CCN L3
  • TSMC 16 nm process
  • 4x DDR4-2400 memory
  • 2-way SMP, Each socket has 2x ports with
96 Gbit/s per port (total of 192 Gbit/s)
  • 46x PCIe 3.0 and 8x 10G Ethernet ports
  • 85 W TBD

Kunpeng 920 (Hi1620)[edit]

The Kunpeng 920 (Hi1620) is HiSilicon's fourth generation server processor

announced in 2018, and launched in 2019. It features:
  • 32 to 64x custom TaiShan V110 cores @ 2.6GHz cores [2]
  • The TaiShan V110 core is a 4-way superscalar, out-of-order
microarchitecture that implements the ARMv8.2-A ISA.
  • The TaiShan V110 cores are likely a new core not based on ARM designs
  • 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3),
2x FSUs (ASIMD FPU), 2x LSUs
  • 64KB L1-I, 64KB L1-D, 512KB Private L2, 1MB L3/core (shared)
  • TSMC 7 nm HPC process
  • 8x DDR4-3200 memory
  • 2-way and 4-way SMP, Each socket has 3x Hydra ports
with 240 Gbit/s per port (total of 720 Gbit/s)
  • 40x PCIe 4.0 with CCIX support, 4x USB 3.0, 2x SATA 3.0,
8x SAS 3.0 and 2x 100G Ethernet ports
  • TBD 100 to 200 W
  • Compression engine (GZIP, LZS, LZ4) capable of up
to 40 Git/s compress and 100 Gbit/s decompress
  • Crypto offload engine (for AES, DES, 3DES, SHA1/2)
capable of throughputs up to 100 Gbit/s

Kunpeng 930 (Hi1630)[edit]

The Kunpeng 930 (Hi1630) is HiSilicon's fifth-generation server processor

announced in 2019 and scheduled for launch in 2021. It features:
  • 80 custom Taishan V120 cores @ 3GHz frequency, with support
for SMT and ARM's Scalable Vector Extension (SVE)
  • 64KB L1-I, 64KB L1-D, 512KB Private L2 and 1MB L3/core (shared)
  • TSMC 5 nm process
  • 8x DDR5 memory

Kunpeng 950[edit]

The Kunpeng 950 is HiSilicon's sixth-generation server processor

announced in 2019 and scheduled for launch in 2023.

References[edit]

  1. ↑ (16 September 2021) Kirin 9000.
  2. ↑ Schor, David (3 May 2019). Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen.
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