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Difference between revisions of "intel/cpuid"
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== CPUIDs== | == CPUIDs== | ||
+ | === Family 19 === | ||
+ | {| class="wikitable" | ||
+ | ! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model | ||
+ | |- | ||
+ | | {{intel|Diamond Rapids|l=arch}} || || 0x4 || 0xF || 0x0 || 0x1 || [[Family 19 Model 1]] | ||
+ | |} | ||
+ | |||
=== Family 15 === | === Family 15 === | ||
{| class="wikitable" | {| class="wikitable" | ||
Line 52: | Line 59: | ||
| rowspan="2" | {{intel|Ice Lake (Client)|l=arch}} || {{intel|Ice Lake U|U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] | | rowspan="2" | {{intel|Ice Lake (Client)|l=arch}} || {{intel|Ice Lake U|U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] | ||
|- | |- | ||
− | | {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || | + | | {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] |
|- | |- | ||
| rowspan="2" | {{intel|Comet Lake|l=arch}} || {{intel|Comet Lake S|S|l=core}}, {{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || [[Family 6 Model 165]] | | rowspan="2" | {{intel|Comet Lake|l=arch}} || {{intel|Comet Lake S|S|l=core}}, {{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || [[Family 6 Model 165]] | ||
Line 133: | Line 140: | ||
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model | ! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model | ||
|- | |- | ||
− | | {{intel| | + | | {{intel|Granite Rapids|l=arch}} || || || || || || |
|- | |- | ||
− | | {{intel| | + | | {{intel|Emerald Rapids|l=arch}} || ? || 0 || 0x6 || 0xC || 0xF || [[Family 6 Model 207]] |
|- | |- | ||
| {{intel|Sapphire Rapids|l=arch}} || ? || 0 || 0x6 || 0x8 || 0xF || [[Family 6 Model 143]] | | {{intel|Sapphire Rapids|l=arch}} || ? || 0 || 0x6 || 0x8 || 0xF || [[Family 6 Model 143]] |
Latest revision as of 07:55, 18 October 2024
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
- AMD's CPUIDs
- Intel's CPUIDs
Modes
Extensions(all)
Below is a list of Intel's CPUID broken down by their respective core names and microarchitecture:
Contents
CPUIDs[edit]
Family 19[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Diamond Rapids | 0x4 | 0xF | 0x0 | 0x1 | Family 19 Model 1 |
Family 15[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Netburst | 0 | 0xF | 0x0 | 0x6 | Family 15 Model 6 | |
Prescott | 0 | 0xF | 0x0 | 0x4 | Family 15 Model 4 | |
Prescott | 0 | 0xF | 0x0 | 0x3 | Family 15 Model 3 | |
Northwood | 0 | 0xF | 0x0 | 0x2 | Family 15 Model 2 | |
Willamette | 0 | 0xF | 0x0 | 0x1 | Family 15 Model 1 |
Family 11[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Knights Ferry | 0 | 0xB | 0x0 | 0x0 | Family 11 Model 0 | |
Knights Corner | 0 | 0xB | 0x0 | 0x1 | Family 11 Model 1 |
Family 6[edit]
Big Cores (Client)[edit]
Intel's client big cores refers to Intel mainstream SoCs that ship in most tablets, laptops, and desktop devices.
Big Cores (Server)[edit]
Intel's server big cores refers to Intel workstation and data center SoCs that ship in most enterprise desktops, workstations, and servers.
Small Cores[edit]
Intel's client small cores refers to Intel low-power SoCs that ship in low power laptops, tablets, embedded devices, and low-power servers.
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Tremont | Jasper Lake | 0 | 0x6 | 0x9 | 0xC | Family 6 Model 156 |
Elkhart Lake | 0 | 0x6 | 0x9 | 0x6 | Family 6 Model 150 | |
Lakefield | 0 | 0x6 | 0x8 | 0xA | Family 6 Model 138 | |
Goldmont Plus | Gemini Lake | 0 | 0x6 | 0x7 | 0xA | Family 6 Model 122 |
Goldmont | Denverton | 0 | 0x6 | 0x5 | 0xF | Family 6 Model 95 |
Apollo Lake, |
0 | 0x6 | 0x5 | 0xC | Family 6 Model 92 | |
Airmont | Cherry Trail, Braswell | 0 | 0x6 | 0x4 | 0xC | Family 6 Model 76 |
Silvermont | SoFIA | 0 | 0x6 | 0x5 | 0xD | Family 6 Model 93 |
Anniedale | 0 | 0x6 | 0x5 | 0xA | Family 6 Model 90 | |
Avoton, Rangeley | 0 | 0x6 | 0x4 | 0xD | Family 6 Model 77 | |
Tangier | 0 | 0x6 | 0x4 | 0xA | Family 6 Model 74 | |
Bay Trail | 0 | 0x6 | 0x3 | 0x7 | Family 6 Model 55 | |
Saltwell | Cedarview | 0 | 0x6 | 0x3 | 0x6 | Family 6 Model 54 |
Cloverview | 0 | 0x6 | 0x3 | 0x5 | Family 6 Model 53 | |
Penwell | 0 | 0x6 | 0x2 | 0x7 | Family 6 Model 39 | |
Bonnell | Lincroft | 0 | 0x6 | 0x2 | 0x6 | Family 6 Model 38 |
Silverthorne, Diamondville, Pineview | 0 | 0x6 | 0x1 | 0xC | Family 6 Model 28 |
MIC Architecture[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Knights Mill | 0 | 0x6 | 0x8 | 0x5 | Family 6 Model 133 | |
Knights Landing | 0 | 0x6 | 0x5 | 0x7 | Family 6 Model 87 |
Family 5[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
Lakemont | Quark | 0 | 0x5 | 0x0 | 0xA | Family 5 Model 10 |
0 | 0x5 | 0x0 | 0x9 | Family 5 Model 9 | ||
P5 | P55C (Mobile) | 0 | 0x5 | 0x0 | 0x8 | Family 5 Model 8 |
0 | 0x5 | 0x0 | 0x7 | Family 5 Model 7 | ||
P55C | 0 | 0x5 | 0x0 | 0x4 | Family 5 Model 4 | |
P54CS | 0 | 0x5 | 0x0 | 0x2 | Family 5 Model 2 | |
P5, P54, P54CQS | 0 | 0x5 | 0x0 | 0x1 | Family 5 Model 1 |
Family 4[edit]
Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
---|---|---|---|---|---|---|
80486 | 0 | 0x4 | 0x0 | 0x9 | Family 4 Model 9 | |
80486DX4 | 0 | 0x4 | 0x0 | 0x8 | Family 4 Model 8 | |
0 | 0x4 | 0x0 | 0x7 | Family 4 Model 7 | ||
0 | 0x4 | 0x0 | 0x5 | Family 4 Model 5 | ||
80486SL | 0 | 0x4 | 0x0 | 0x4 | Family 4 Model 4 | |
80486DX2 | 0 | 0x4 | 0x0 | 0x3 | Family 4 Model 3 | |
80486SX | 0 | 0x4 | 0x0 | 0x2 | Family 4 Model 2 | |
80486DX | 0 | 0x4 | 0x0 | 0x1 | Family 4 Model 1 |